We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64719

2015.1 Vivado MIG DDR3 - [Place 30-805] IODELAY_GROUP needs BITSLICE_CONTROL to calibrate to many I/O, 16 versus 7


A case has been seen where a design that successfully implemented in Vivado 2014.4, now fails with the following error in the Placer in Vivado 2015.1.

ERROR: [Place 30-805] IODELAY_GROUP XIL_INTERNAL_IDC_GROUP_1 requires BITSLICE_CONTROL instance u_mig_48/inst/u_ddr3_mem_intfc/u_mig_ddr3_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control to calibrate 61 I/O delay instances (listed below).
In mixed mode, a bitslice control can only calibrate a maximum of 7 I/O delay instances such that they can all fit into a nibble in an I/O bank.
Please review and modify the IODELAY_GROUP constraints.
List of I/O delays as part of the IODELAY_GROUP:

Is this a known issue? 

Is there a work-around?


This error can be due to a known issue in the placer.

If no IODELAY_GROUP has been defined, the placer will build one automatically.

The issue is that this default group can be built incorrectly.

This has been fixed for Vivado 2015.3.

In the meantime, the work-around is to define a valid IODELAY_GROUP with XDC constraints to prevent the placer from building the incorrect group.

AR# 64719
Date Created 06/02/2015
Last Updated 07/28/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1