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AR# 64734

2015.1 Partial Reconfiguration - Too many logic cells are blocked in the second RM implementation causing a place error, even if the RM1 and RM2 share the same netlist file

Description

There is only one Reconfigurable Partition (RP) in my Partial Reconfiguration design.

I am using the same netlist file for 2 Reconfigurable Modules (RM1 and RM2) of the RP.

The first RM implementation completes without error.

I carve RM1 and import the netlist of RM2.

In the second RM implementation, I receive the following error in place:

Phase 2 Global Placement
ERROR: [Place 30-504] Global clock placer failed to legalize CLOCKREGION_X0Y7 for clock loads of type DSP48E1. This region contains 120 available DSP48E1 sites,
however there are 526 such loads in the region and clock legalizer could not move enough loads out of the region to legalize it.
The following clock nets have loads of type DSP48E1 in this region:
Clock net: ext_clk.pipe_clock_i/CLK_USERCLK2
Driver: ext_clk.pipe_clock_i/userclk2_i1.usrclk2_i1
Number of DSP48E1 loads: 120

After setting the skipUtilizationCheck parameter and rerunning placement, I see a new place error.

For Example:

set_param place.skipUtilizationCheck 1


ERROR: [Place 30-818] Some BRAM area constraints are over utilized.

148 or more BRAMs failed to place.

Some BRAM sites are excluded by the following pblocks. Check whether sufficient sites exist for BRAM instances not included in the exclude pblocks.

Exclude pblock 'pblock_reconfig_module': with ranges:

RAMB36_X10Y60:RAMB36_X11Y79

The unplaced BRAMs are constrained as below: (listing maximum of 20 BRAMs per constraint)

Pblock 'pblock_reconfig_module':

Pblock ranges:

RAMB36_X10Y60:RAMB36_X11Y79

RAMB36_X10Y0:RAMB36_X11Y39

RAMB36_X1Y0:RAMB36_X9Y79

RAMB18_X10Y120:RAMB18_X11Y159

RAMB18_X10Y0:RAMB18_X11Y79

RAMB18_X1Y0:RAMB18_X9Y159

DSP48_X11Y120:DSP48_X11Y159

DSP48_X11Y0:DSP48_X11Y79

DSP48_X0Y0:DSP48_X10Y159

m

_module/unit_pe/sram_B_7_1/U0/inst_blk_mem_gen/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram

Number of BRAMs required by this constraint: 508

Number of BRAMs available in this constraintregion: 275

Utilization= 184%

The original available BRAM in 'pblock_reconfig_module is 1880, much more than 275.

Why does it occur?

Solution

The root cause for this issue is that many BRAMs and DSPs are blocked unexpectedly during the first configuration.

You can try the following two work-arounds:

1. Avoid using the Explore directive in the route_design of the first configuration and avoid using post-route phys_opt_design.

2. Set the parameter place.closeImportedSites to false before route_design with the Explore directive in the first configuration.

For Example:

set_param place.closeImportedSites false

The issue is fixed in Vivado 2015.3.

Linked Answer Records

Associated Answer Records

AR# 64734
Date Created 06/03/2015
Last Updated 06/15/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.1