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AR# 64743

UltraScale IODELAY - Explanation of clock alignment delay


If I read the CNTVALUEOUT of an IDELAYE3 or an ODELAYE3 with DELAY_FORMAT = TIME and DELAY_VALUE = 0, the value read out is a non zero value. 

Why does this occur?


During calibration, the IDELAYCTRL / BITSLICE_CONTROL will measure the clock alignment delay which is the difference in the delays between the data path and the clock path to the capture flip-flop (IDDR, ISERDES, RX_BITSLICE), i.e. the difference in the paths between D and C ports in the diagram below.

The clock alignment delay should be between 50 and 60 Taps with an average of 54 Taps.

The IDELAY applies this clock alignment delay to the delay so that the paths are balanced.

If you set your DELAY_VALUE = 500ps the total amount of TAPs used will also include the clock alignment delay. 

If you are calculating the Tap size you may want to remove the clock alignment portion of the delay.

You can either measure the clock alignment by having a DELAY_VALUE = 0 during calibration and reading out the resulting CNTVALUEOUT or use the average of 54 Taps. 

For example DELAY_VALUE = 500ps and CNTVALUEOUT = 160.

Tap size = 500 / (160-54) = 4.72ps

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
60802 UltraScale - How to calculate the size of TAP in IDELAY & ODELAY N/A N/A
AR# 64743
Date Created 06/05/2015
Last Updated 06/10/2015
Status Active
Type General Article
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