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AR# 64749

LogiCORE IP JESD204 PHY v2.0 - CPLLPD not correctly set


For the JESD204 PHY v2.0 (2015.1), when using the QPLL with the AXI4-Lite Management Interface option turned ON in the GUI, the CPLLPD port is set to 0 by default.

This can result in a current surge on the MGTAVTT power rail, as described in (Xilinx Answer 59294).


Due to the potential power spike, as described in (Xilinx Answer 59294), the CPLLPD must be set to 1 (regardless of whether it is being used or not).

To work around this issue for the JESD204 PHY v2.0 (2015.1), the recommendation is to manually make changes to the CPLL_PD initial value (see jesd204_phy_10g_axi_transDbgCtrl_async.v module), and set it to 1.

This has been fixed in JESD PHY v2.0 (Rev. 1) for Vivado 2015.2, as outlined in the IP Change Log:

  • Removed redundant CPLL reset logic for 7 Series. This input was being ignored by the Transceiver. Controlled by internal state machines.
  • Added logic to create a reset pulse if PLL LOCK is lost. 7 Series only.
  • Fixed issue with CPLLPD and QPLLPD default values when AXI4-Lite Management Interface is enabled. PLLs are powered down if not enabled.
AR# 64749
Date 12/04/2015
Status Active
Type General Article
  • Kintex-7
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • JESD204
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