UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64754

Vivado 2014.3 Block memory Generator - Simulation mismatch In BLOCK Memory Generator in SPD mode with ECC

Description

In the Block Memory Generator v8.2, if SPD mode with ECC is used, there is a difference between behavioral simulation and Post-synthesis Functional simulation.

Solution

An enhancement in Vivado 2014.3 improves the power consumption at the BRAM primitive.

For the Block memory generator core in SPD mode with ECC, WEA is not used for a write operation any longer and ENA should be used instead.

However, this change has not been reflected in the behavioral simulation model.

As a result, the WEA port still works as in the earlier version of the core.

The model has been fixed in Vivado 2015.3.

As a work-around, WEA should be asserted with ENA for a write operation as described in Figure 3-30 of (PG058) April 1, 2015.

AR# 64754
Date Created 06/08/2015
Last Updated 02/02/2016
Status Active
Type General Article
IP
  • Block Memory Generator