UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64761

Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration

Description

This answer record provides a PDF document describing bitstream loading across the PCI Express Link for Tandem PCIe or Partial Reconfiguration solutions.

The associated files have also been provided in a ZIP file.

The provided mechanism to load bitstreams is applicable for UltraScale Architecture Gen3 Integrated Block for PCI Express cores. 

This mechanism will allow users to deliver via MCAP Tandem Stage 2 bitstreams, clearing bitstreams, and partial bitstreams for Tandem Configuration and/or Partial Reconfiguration designs.

For tandem PCIe second stage bitstream loading across the PCI Express Link on 7 Series devices, please refer to (Xilinx Answer 51950).

Solution

Please download the "Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration"  PDF and the associated design files at the end of this answer record.

The file names are:

  • Xilinx_Answer_64761_UltraScale_Devices.pdf
  • Xilinx_Answer_64761_Files.zip

Revision History:

06/30/2015 - Initial release
10/06/2015 - Updated for 'Tandem Field Update'

Attachments

Associated Attachments

AR# 64761
Date Created 06/09/2015
Last Updated 11/10/2015
Status Active
Type General Article
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)