SETUP/HOLD violations might be seen on the following paths (or similar paths) for MIG UltraScale DDR4 designs:

Slack -0.069ns
Source u_sdram1/u_ddr4_ctrl/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_mc_cal/u_ddr_mc_pi/u_ddr_mc_write/wrQ_reg[1][0]/C   (rising edge-triggered cell FDRE clocked by mmcm_clkout0_1  {rise@0.000ns fall@2.500ns period=5.000ns})
Destination u_sdram1/u_ddr4_ctrl/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_mc_cal/u_ddr_cal/u_ddr_cal_addr_decode/cal_DQ_reg[421]/D   (rising edge-triggered cell FDRE clocked by mmcm_clkout0_1  {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group mmcm_clkout0_1
Path Type Setup (Max at Slow Process Corner)
Requirement 5.000ns (mmcm_clkout0_1 rise@5.000ns - mmcm_clkout0_1 rise@0.000ns)
Data Path Delay 4.816ns (logic 0.593ns (12.313%)  route 4.223ns (87.687%))
Logic Levels 4  (LUT3=3 LUT6=1)
Clock Path Skew -0.257ns
Clock Uncertainty 0.057ns
Clock Net Delay (Source) 3.212ns (routing 1.417ns, distribution 1.795ns)
Clock Net Delay (Destination) 2.845ns (routing 1.304ns, distribution 1.541ns)

 

Slack (Hold) -0.324ns
Source u_sdram0/u_ddr4_ctrl/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_mc_cal/u_ddr_cal/u_ddr_cal_addr_decode/cal_RAS_A_reg[4]/C   (rising edge-triggered cell FDSE clocked by riu_clk  {rise@0.000ns fall@5.000ns period=10.000ns})
Destination u_sdram0/u_ddr4_ctrl/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_mc_cal/u_ddr_cal/u_ddr_cal_addr_decode/cal_RAS_pre_reg[4]/D   (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group mmcm_clkout0
Path Type Hold (Min at Slow Process Corner)
Requirement 0.000ns (mmcm_clkout0 rise@0.000ns - riu_clk rise@0.000ns)
Data Path Delay 0.665ns (logic 0.161ns (24.211%)  route 0.504ns (75.789%))
Logic Levels 1  (LUT3=1)
Clock Path Skew 0.825ns
Clock Uncertainty 0.057ns
Clock Net Delay (Source) 1.690ns (routing 0.326ns, distribution 1.364ns)
Clock Net Delay (Destination) 2.467ns (routing 0.836ns, distribution 1.631ns)