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AR# 64784

MIG UltraScale DDR4 - false DRC MIG-32# errors detected for sys_clk_p/n

Description

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

Under some circumstances, the following false DRC errors might be reported when running "report_drc" on a synthesized checkpoint:

MIG-32#1 Error
Auto Assignment
[c0_sys_clk_p, c0_sys_clk_n] Unable to find the required number (%STR) of consecutive empty bank(s) to auto place all the memory bytes.
Related violations: <none>
MIG-32#2 Error
Auto Assignment
[c0_sys_clk_p, c0_sys_clk_n] Unable to find the required number (%STR) of consecutive empty bank(s) to auto place all the memory bytes.
Related violations: <none>
MIG-32#3 Error
Auto Assignment
[c0_sys_clk_p, c0_sys_clk_n] Unable to find the required number (%STR) of consecutive empty bank(s) to auto place all the memory bytes.
Related violations: <none>

Solution

If it is determined these error messages are false, then they can be safely ignored by changing the message SEVERITY to a warning instead of an error.

Tcl Syntax:

set_property SEVERITY {Warning} [get_drc_checks MIG-32]

Revision History:

06/30/2015 - Initial Release

AR# 64784
Date Created 06/11/2015
Last Updated 10/23/2015
Status Active
Type Known Issues
Devices
  • Virtex UltraScale
IP
  • MIG UltraScale