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AR# 64788

UltraScale RX_BITSLICE - Q output changes even though the FIFO_RD_EN is not asserted


In simulation and hardware is is observed that if the FIFO_RD_EN is held low, the output of the FIFO will change every 8 FIFO_RDCLK cycles.


The diagram below shows the data written to the FIFO.

If the FIFO_RD_EN is not high, the first data stays at the Q output while the FIFO is filled with data.

When the FIFO rolls over, new data is written to position 0 but also passed to the Q output.

When the FIFO loops around, the EMPTY flag wil also pulse from LOW to HIGH.




AR# 64788
Date Created 06/12/2015
Last Updated 06/12/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale