UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64793

Design Advisory for Aurora 8B10B v11.0 (or) earlier - Artix-7 GTP - Simplex RX core is not de-asserting MMCM Reset and as a result RXRESETDONE is not HIGH

Description

This issue is observed only when an Aurora 8B10B core is configured with 4-byte interface width and Simplex RX data flow mode targeting Artix-7 GTP. 

The input to RXOUTCLK connecting to RX_STARTUP_FSM is sourced by user_clk which is MMCM output (input is txoutclk). 

Reset to MMCM is driven from RX_STARTUP_FSM and it is being driven based on an RXPMARESETDONE signal synchronized to RXOUTCLK. Negedge detection is being done.

Solution

This issue is fixed in Aurora 8B10B v11.0 Rev1 core released with VIVADO 2015.2 tool version.

To fix this issue with earlier core versions (v11.0 or earlier), please update the following files.

  • <component_name>_wrapper.v[hd]
  • <component_name>_multi_gt.v[hd]
  • <component_name>_gt.v[hd]
  • <component_name>_rx_startup_fsm.v[hd]
  • <component_name>_clocks.xdc

===========================================================================

Verilog:

===========================================================================

<component_name>_wrapper.v:

Declare the following wires

 wire              gt0_txpmaresetdone_o;
 wire              gt_txpmaresetdone_i;
 wire              gt_txoutclk_out;

1. Instantiate a BUFH on the TXOUTCLK1_OUT signal as shown below.

Updates:

       BUFH rxout0_buf
           (.O   (gt_txoutclk_out),
            .I   (TXOUTCLK1_OUT));

2. Connect the output of the BUFH instantiated in step 1 to the RXOUTCLK input of the RX_STARTUP_FSM instantiation.

From

.RXOUTCLK                       (RXUSRCLK2_IN),

To

.RXOUTCLK                       (gt_txoutclk_out),

3. For the <component_name>_multi_gt module instantiation, a new port connection is required.

.gt0_txpmaresetdone_out             (gt0_txpmaresetdone_o),

 

The code snippet above shows a single lane use case.

For multi-lane scenario, port connections need to be added based on the number of lanes.

In a 2-lane scenario for example, the following will be the code snippet.

.gt0_txpmaresetdone_out             (gt0_txpmaresetdone_o),
.gt1_txpmaresetdone_out             (gt1_txpmaresetdone_o),

 

4. Connect gt_txpmaresetdone_i to the RXPMARESETDONE input of the RX_STARTUP_FSM instantiation.

assign gt_txpmaresetdone_i  = gt0_txpmaresetdone_o;

The code snippet above is for a single lane use case. 

For a multi-lane scenario, txpmaresetdone port connections from each lane need to be ANDed together and assigned to gt_txpmaresetdone_i.

In a 2-lane scenario for example, the following will be the code snippet:

assign gt_txpmaresetdone_i  = gt0_txpmaresetdone_o && gt1_txpmaresetdone_o ;

From:

RXPMARESETDONE                 (tied_to_vcc_i),

To:

RXPMARESETDONE                 (gt_txpmaresetdone_i), 

<component_name>_multi_gt.v:

1. Declare a new output port for the gt0_txpmaresetdone_out signal:

output          gt0_txpmaresetdone_out,

2. For the <component_name>_gt module instantiation, a new port connection is required:

.txpmaresetdone_out             (gt0_txpmaresetdone_out),

The code snippet above is for a single lane use case. 

For multi-lane scenarios, port connections need to be added based on the number of lanes. 

In a 2-lane scenario for example, the following will be the code snippet.

From <component_name>_gt_inst:

.txpmaresetdone_out             (gt0_txpmaresetdone_out),

From <component_name>_gt_inst_lane1:

.txpmaresetdone_out             (gt1_txpmaresetdone_out),

<component_name>_gt.v:

1. Declare a new output port for the txpmaresetdone_out signal:

Update:

output          txpmaresetdone_out,

 

2. For the GTPE2_CHANNEL component instantiation, update the port connection to the TXPMARESETDONE output port

From

.TXPMARESETDONE               (),

To

.TXPMARESETDONE               (txpmaresetdone_out),

 

<component_name>_rx_startup_fsm.v:

This module requires the following code edits.

1. Update the rxpmaresetdone_i related circuit.

Update the following assignment on line 269:

From:

rxpmaresetdone_i <= `DLY pmaresetdone_fallingedge_detect_s & rxpmaresetdone_rx_s;

To:

rxpmaresetdone_i <= `DLY rxpmaresetdone_rx_s;

2. Update the data_valid_sync related circuit.

Remove the <component_name>_cdc_sync synchronizer and assign a DATA_VALID signal to data_valid_sync on line 591.

From:

aurora_8b10b_0_cdc_sync
  #(
     .c_cdc_type      (1             ),  
     .c_flop_input    (0             ), 
     .c_reset_state   (0             ), 
     .c_single_bit    (1             ),  
     .c_vector_width  (2             ), 
     .c_mtbf_stages   (3              ) 
   )sync_data_valid_cdc_sync 
   (
     .prmry_aclk      (RXUSERCLK                  ),
     .prmry_rst_n     (1'b1                       ),
     .prmry_in        (DATA_VALID                 ),
     .prmry_vect_in   (2'd0                       ),
     .scndry_aclk     (STABLE_CLOCK               ),
     .scndry_rst_n    (1'b1                       ),
     .prmry_ack       (                           ),
     .scndry_out      (data_valid_sync            ),
     .scndry_vect_out (                           )
    );

To:

assign data_valid_sync = DATA_VALID;

===========================================================================

VHDL:

===========================================================================

<component_name>_wrapper.vhd:
 
1. Update the component instantiation.

Add a GT0_TXPMARESETDONE_OUT port to the <component_name>_multi_gt component.

 

GT0_TXPMARESETDONE_OUT                  : out  std_logic;

 

2. Instantiate the BUFH component:

 component BUFH
        port (
                O : out std_ulogic;
                I : in  std_ulogic
             );
    end component;
3. Declare the following signals:

 signal gt0_txpmaresetdone_o : std_logic;
 signal TXOUTCLK_OUT : std_logic;
 signal gt_txpmaresetdone_i : std_logic;
 signal gt_txoutclk_out     : std_logic;

 

4. Update the connection to the GT0_TXOUTCLK_OUT port of the <component_name>_multi_gt instantiation.

From

 GT0_TXOUTCLK_OUT          =>  TXOUTCLK1_OUT

To

 GT0_TXOUTCLK_OUT          =>  TXOUTCLK_OUT,

 

5. For the <component_name>_multi_gt module instantiation, a new port connection is required:

gt0_txpmaresetdone_out             => gt0_txpmaresetdone_o,

 

The code snippet above is for a single lane use case. 

For multi-lane scenarios, port connections need to be added based on the number of lanes. 

In a 2-lane scenario for example, the following will be the code snippet.

 gt0_txpmaresetdone_out             => gt0_txpmaresetdone_o,
 gt1_txpmaresetdone_out             => gt1_txpmaresetdone_o,

 

6. Signal assignments:

 TXOUTCLK1_OUT       <= TXOUTCLK_OUT;
 gt_txpmaresetdone_i  <= gt0_txpmaresetdone_o; 

 

The code snippet above for gt_txpmaresetdone_i is for a single lane use case.

For a multi-lane scenario, txpmaresetdone port connections from each lane need to be ANDed together and assigned to gt_txpmaresetdone_i.

In a 2 lane scenario for example, the following will be the code snippet.

gt_txpmaresetdone_i  <= gt0_txpmaresetdone_o AND gt1_txpmaresetdone_o; 

 

 

7. Instantiate a BUFH on the TXOUTCLK_OUT signal as shown below:
 

 rxout0_buf : BUFH
  port map
   (O =>  gt_txoutclk_out,
    I =>  TXOUTCLK_OUT); 

 

8. Connect the output of the BUFH instantiated in step 5 to the RXOUTCLK input port of the RX_STARTUP_FSM instantiation.

From:

 RXOUTCLK                       => RXUSRCLK2_IN,

To:

 RXOUTCLK                       => gt_txoutclk_out

 

9. Connect gt_txpmaresetdone_i to the RXPMARESETDONE input of the RX_STARTUP_FSM instantiation.

From:
 

RXPMARESETDONE                 => tied_to_vcc_i, 

To:

RXPMARESETDONE                 => gt_txpmaresetdone_i

 

<component_name>_multi_gt.vhd:

1. Declare a new output port for the TXPMARESETDONE_OUT signal.

GT0_TXPMARESETDONE_OUT                  : out  std_logic;

 

2. Update the component instantiation.

Add aTXPMARESETDONE_OUT port to <component_name>_gt.

TXPMARESETDONE_OUT                  : out  std_logic;

 

3.  For <component_name>_gt module instantiation, a new port connection is required.

TXPMARESETDONE_OUT              =>      GT0_TXPMARESETDONE_OUT,

 

The code snippet above is for a single lane use case. 

For multi-lane scenarios, port connections need to be added based on the number of lanes. 

In a 2-lane scenario for example, the following will be the code snippet.

From <component_name>_gt_inst:

TXPMARESETDONE_OUT              =>      GT0_TXPMARESETDONE_OUT,

 

From <component_name>_gt_inst_lane1:

TXPMARESETDONE_OUT              =>      GT1_TXPMARESETDONE_OUT,

 

<component_name>_gt.vhd:

1. Declare a new output port for the TXPMARESETDONE_OUT signal:

TXPMARESETDONE_OUT                      : out  std_logic;

 

2. Signal declaration:

signal    txpmaresetdone_t                : std_logic;

 

3. For the GTPE2_CHANNEL component instantiation, update the port connection to the TXPMARESETDONE output port.

From:

TXPMARESETDONE                  =>      open,

To:

TXPMARESETDONE                  =>      txpmaresetdone_t,

 

4. Signal assignment.

TXPMARESETDONE_OUT    <=   txpmaresetdone_t;

 

<component_name>_rx_startup_fsm.vhd:

This module requires the following code edits:

1. Update the rxpmaresetdone_i related circuit.

Update the following assignment on line 263:

From:
 

rxpmaresetdone_i <= pmaresetdone_fallingedge_detect_s and rxpmaresetdone_rx_s;

To:
 

rxpmaresetdone_i <= rxpmaresetdone_rx_s;

 

2. Update the data_valid_sync related circuit.

Remove the <component_name>_cdc_sync synchronizer and assign the DATA_VALID signal to data_valid_sync on line 610.

From:
 

sync_data_valid_cdc_sync : aurora_8b10b_1_cdc_sync
generic map
   (
     c_cdc_type      => 1             ,   
     c_flop_input    => 0             , 
     c_reset_state   => 0             , 
     c_single_bit    => 1             , 
     c_vector_width  => 2             , 
     c_mtbf_stages   => 3  
   )
port map  
   (
     prmry_aclk      => RXUSERCLK                         ,
     prmry_resetn    => '1'                               ,
     prmry_in        => DATA_VALID                        ,
     prmry_vect_in   => "00"                              ,
     scndry_aclk     => STABLE_CLOCK                      ,
     scndry_resetn   => '1'                               ,
     prmry_ack       => open                              ,
     scndry_out      => data_valid_sync                   ,
     scndry_vect_out => open 
    );

To:

data_valid_sync <= DATA_VALID;

 ===========================================================================

Update to <component_name>_clocks.xdc

Make the following change:

From

set_false_path -through [get_pins -hier *cdc_to*]

To

set_false_path -to [get_pins -hier *cdc_to*]

 

Revision History:

08/03/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
51553 Design Advisory Master Answer Record for LogiCORE IP Aurora 8B10B and Aurora 64B66B N/A N/A
AR# 64793
Date Created 06/15/2015
Last Updated 08/17/2015
Status Active
Type Design Advisory
Devices
  • Artix-7
Tools
  • Vivado Design Suite - 2015.1
IP
  • Aurora 8B/10B