UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64808

7 Series Integrated Block for PCI Express v3.1 - Enable Slot Clock Configuration GUI option and PCIE_ASYNC_EN parameter

Description

I am using the 7 Series Integrated Block for PCI Express v3.1.

I have disabled the 'Enable Slot Clock Configuration' option in the Advanced Mode configuration GUI under the 'Link Registers' tab.

The source code 'PCIE_ASYNC_EN' parameter is set to TRUE when I do this.

Which file contains this parameter?

Solution

This parameter 'PCIE_ASYNC_EN' is set to TRUE in the 'pcie_7x_0_core_top.v' source file.

Revision History
06/16/2015
AR# 64808
Date Created 06/16/2015
Last Updated 06/17/2015
Status Active
Type General Article
IP
  • 7 Series Integrated Block for PCI Express (PCIe)