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AR# 64839

Zynq-7000 AP SoC Cache invalidate - Is it recommended to do an invalidate before/after initiating a DMA transfer?

Description

According to ARM references, an invalidate should be done before a memory range affected by an incoming DMA transfer is accessed.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0228a/index.html

Is it recommended to do an invalidate before/after initiating a DMA transfer?


I am running a SMP VxWorks system on cortex A-9 with non-exclusive cache configuration. 

I can see the cache invalidate failure.

The Software flow is -

  1. Cache Invalidate
  2. DMA transfer
  3. Copy data

If I add an invalidate sequence after DMA is done, there will be no cache invalidate failure.

Software flow is -

  1. Cache Invalidate
  2. DMA transfer
  3. Cache Invalidate
  4. Copy data


If speculative prefetching is enabled the CPU *might* fetch some cache lines while DMA transfer is going on, leading to data corruption.

However if I try to disable speculative prefetching in the ACTLR register using the following settings, Cache invalidate still fails:

ACTLR=0x41 (which mean non-exclusive), prefetching is disabled for L1/L2



My cache invalidate sequence is following the ARM's suggestion.

The robust code sequence for invalidation with a non-exclusive cache arrangement is:

  • InvalLevel2 Address - forces the address out past level 2
  • CACHE SYNC - Ensures completion of the L2 inval
  • InvalLevel1 Address - This is broadcast within the cluster
  • DSB - Ensure completion of the inval as far as Level 2.

If the reason is not speculative pre-fetching, what can cause this behavior?

Solution

The bits in the ACTLR disable particular forms of speculation - they do not globally disable speculation.

Therefore it is quite possible you are still seeing speculation.

The ARMv7-A/R Architecture Reference Manual gives example sequences in Appendix D7 (Barrier Litmus Tests).

However, the expected sequence would be similar to the following:

  • <invalidate cache by VA to PoC> <-- Remove any potentially dirty lines
  • DSB <-- Assumes DMA started by write to memory mapped register
  • <initiate DMA>
  • <wait for DMA completion>
  • DMB <-- Assumes the DMA is being polled
  • <invalidate cache by VA to PoC> <-- Ensures contents of caches from after DMA
  • DMB
AR# 64839
Date Created 06/23/2015
Last Updated 07/21/2015
Status Active
Type General Article
Devices
  • Zynq-7000