According to ARM references, an invalidate should be done before a memory range affected by an incoming DMA transfer is accessed.
Is it recommended to do an invalidate before/after initiating a DMA transfer?
I am running a SMP VxWorks system on cortex A-9 with non-exclusive cache configuration.
I can see the cache invalidate failure.
The Software flow is -
If I add an invalidate sequence after DMA is done, there will be no cache invalidate failure.
Software flow is -
If speculative prefetching is enabled the CPU *might* fetch some cache lines while DMA transfer is going on, leading to data corruption.
However if I try to disable speculative prefetching in the ACTLR register using the following settings, Cache invalidate still fails:
ACTLR=0x41 (which mean non-exclusive), prefetching is disabled for L1/L2.
My cache invalidate sequence is following the ARM's suggestion.
The robust code sequence for invalidation with a non-exclusive cache arrangement is:
If the reason is not speculative pre-fetching, what can cause this behavior?