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AR# 64841

AXI Ethernet v3.01 - Clock domain crossing constraints generated in the core NCF can cause timing analysis to be ignored for the whole chip by the tool

Description

With AXI Ethernet v3.01 IP in XPS, the following constraints will be automatically generated in the core UCF:

TIMESPEC "TS_axi_ethernet_0_AXI4LITE_CLK_2_GTX_CLK" = FROM "axi4lite_clk" TO "clk_gtx" 8000 ps DATAPATHONLY;

TIMESPEC "TS_axi_ethernet_0_GTX_CLK_2_AXI4LITE_CLK" = FROM "clk_gtx" TO "axi4lite_clk" 10000 PS DATAPATHONLY;

If I connect AXI4Lite and GTX_CLK to the same clock source externally (sys_clk), the tool does not recognize this, resulting in all sys_clk paths being analyzed by the by the DATAPATHONLY timespec.

See the following example from the timing report:

Timing constraint: TS_axi_ethernet_0_GTX_CLK_2_AXI4LITE_CLK = MAXDELAY FROM 

TIMEGRP "clk_gtx" TO TIMEGRP "axi4lite_clk" 10 ns DATAPATHONLY;

520064 paths analyzed, 28829 endpoints analyzed, 0 failing endpoints

 

As shown in the figure below, the IP constraints include a DATAPATHONLY timespec to constrain the CDC timing path between clk1 and clk2. 

 

 

 

64841.png



I have connected the IP clk1 and clk2 to the same top-level clock (sys_clk). 

As a result, the DATAPATHONLY timespec get applied to the whole sys_clk domain.

The reg1-to-reg2 path get constrained by the DATAPATHONLY timespec and not by the sys_clk clock constraints.


 

 

 

Solution

To avoid this issue, follow the steps below:

1) Run Synthesis for the design.

2) After Synthesis completes, comment out the following constraints n the generated ncf file, mb_0_framework_axi_ethernet_0_wrapper.ncf:

#TIMESPEC "TS_axi_ethernet_0_AXI4LITE_CLK_2_GTX_CLK" = FROM "axi4lite_clk" TO "clk_gtx" 8000 ps DATAPATHONLY;

#TIMESPEC "TS_axi_ethernet_0_GTX_CLK_2_AXI4LITE_CLK" = FROM "clk_gtx" TO "axi4lite_clk" 10000 PS DATAPATHONLY;

3) Continue running the implementation.

AR# 64841
Date Created 06/23/2015
Last Updated 06/29/2015
Status Active
Type General Article
Tools
  • EDK - 14.7
IP
  • AXI Ethernet