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AR# 64842

1G/2.5G Ethernet PCS/PMA or SGMII v15.0 (Rev1) or earlier - LVDS Transceiver - Soft reset may cause data corruption in LVDS Transceiver

Description

When I am sweeping the external delay (external loopback latency) to the LVDS transceiver, the link will come up after multiple soft resets, or sometimes not at all, with rxnotintable and rxdisperr errors.

When comparing txdata and rxdata, I see data corruption as below.

The rxdata starts to differ from the txdata as highlighted in the red box.

 

Capture120150701.PNG

 

Solution

This is an issue with the generation of local_reset in the ten_spd_c2c_serdes_1_to_10_ser8.v file.

 

To fix the issue, please change the following line:

 

 

From:

assign reset_n_idelay_rdy = reset && (~idelay_rdy);

 

To:

assign reset_n_idelay_rdy = reset || (~idelay_rdy);

 

 

 

The reset a is a combination of hard reset and soft reset.

 

In this system ,idelay_rdy is 1.

The above signal "reset_n_idelay_rdy" is used to reset ISERDES and delay controller logic. 

In hardware, the duration for which the hard reset ispressed would be sufficient to reset the idelay_ctrl module, which would immediately dessert the idelay_rdy. 

This would then couple with the reset and trigger reset_n_idelay_rdy. 

 

 

A Reset signal is used to rest the idelay elements.

The rationale behind using two reset signals is that is that idelay elements reset first and the eye logic remain in reset till the time idelay_ctrl is ready.

 

With the original logic, when reset is asserted, only the idelay elements are getting reset, and not the logic associated with finding the optimum sampling point, resulting in the data corruption.

 

This issue is seen when soft reset is used, in which case idelay_ctrl is not reset but idelay are reset.

This issue will be fixed in the 2015.3 release.

AR# 64842
Date Created 06/23/2015
Last Updated 07/02/2015
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII