This design demonstrates how to make the example design working on the KC705 board.
In this example, it simply converts the single ended clock to a differential system clock pair on board, and then adds some debug signals to make all of the Block Memory ports visible in Logic Analyzer.
This design is based on the auto-generated example design, and has been only tested on Vivado 2015.1 and a KC705 board. You can implement it on a custom board by modifying the device type and LOC constraints in the .xdc file.
The Following are all of the changes made to the example design:
1. Make Port A and Port B share the same clock.
2. Use IBUFDS to generate a single end clock, and then drive it to a BUFG.
3. Add LOC constraints to all of the input and output ports.
4. After Synthesis, open the Synthesized design, and create a debug for interested signals, then save the .xdc file.
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