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AR# 64913

1G/2.5G Ethernet PCS/PMA or SGMII - Clock connection for UltraScale Architecture


Figure 3-7 of (PG047) shows the connection between RXUSRCLK/RXUSRCLK2 and RXOUTCLK via BUFG_GT.

However, the example design of the IP for UltraScale devices connects between RXUSRCLK/RXUSRCLK2 and TXOUTCLK through the buffer.

Which is the recommended clock connection?


Figure 3-7 of (PG047) has an incorrect connection.

RXUSRCLK/RXUSRCLK2 should be sourced by TXOUTCLK.

The figure will be corrected in the 2015.3 release of the document.

AR# 64913
Date Created 07/05/2015
Last Updated 07/31/2015
Status Active
Type General Article
  • Ethernet 1000BASE-X PCS/PMA or SGMII