Figure 3-7 of (PG047) shows the connection between RXUSRCLK/RXUSRCLK2 and RXOUTCLK via BUFG_GT.
However, the example design of the IP for UltraScale devices connects between RXUSRCLK/RXUSRCLK2 and TXOUTCLK through the buffer.
Which is the recommended clock connection?
Figure 3-7 of (PG047) has an incorrect connection.
RXUSRCLK/RXUSRCLK2 should be sourced by TXOUTCLK.
The figure will be corrected in the 2015.3 release of the document.