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AR# 64995

Vivado Timing Closure – Suggestions for resolving CDC timing issues


This General Answer Record provides suggestions on how to resolve CDC timing violations seen in Vivado.


Vivado times the paths between all of the clocks in your design by default. As a result you will need to check if any timed CDC path is intended or not.

(A) Timing Violations on Asynchronous CDC

Asynchronous CDC paths usually have high skew and/or unrealistic path requirements. 

We strongly recommend using the Clock Interaction report (report_clock_interaction ) to check the clock relationships.

In general, Asynchronous paths can be disabled when safe asynchronous CDC circuitry is implemented.

Please use set_clock_groups or set_false_path if possible.

(B) Timing Violations on Synchronous CDC

Paths between clocks from different MMCM / PLL can be Safely timed but high skew makes it impractical.

As a result it is recommended to treat them as asynchronous.

Synchronous CDC skew reduction:

Use the same CLOCK_ROOT for both clock nets.

set both CLOCK_ROOTs to the same clock region as the clock with the highest fan-out.

AR# 64995
Date Created 07/16/2015
Last Updated 11/04/2015
Status Active
Type General Article
  • Vivado Design Suite