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AR# 64996

Vivado Constraints - CLOCK_ROOT property cannot be applied to global clock buffer


By default, the place and route tools will automatically assign a clock root to achieve the best timing characteristics for the design.

Using the CLOCK_ROOT property lets you manually assign the clock driver, or root to a specific clock region on the target part, and hence manage clock skew.

(UG912) Vivado Design Suite Properties Reference Guide states that the applicable objects of CLOCK_ROOT can be either a global clock net or global clock buffer driving the clock net.

However, I see the following critical warning if I apply CLOCK_ROOT to a BUFGCE.

[Netlist 29-69] Cannot set property 'CLOCK_ROOT', because the property does not exist for objects of type 'cell'.

How do I correctly apply this property?


The CLOCK_ROOT property can only be assigned to the net segment driven directly by the global clock buffer.

It is illegal to attach it to a global clock buffer.

The document will be corrected in a future version.

If you want to set CLOCK_ROOT using the clock buffer name, follow the syntax example below:

set_property CLOCK_ROOT XnYm [get_nets -of [get_pins bufferName/O]]

AR# 64996
Date 07/31/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
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