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AR# 65044

2015.2 Vivado Timing - PCI-Express (IP Version 4.0) - pulse width switching violations (TPWS) sometimes seen in the PCIE core


In Vivado 2015.2, I sometimes see pulse width switching violations (TPWS) in the PCIE core.


In Vivado 2015.2, we sometimes see pulse width switching violations (TPWS) in the PCIE core.

There was a change to the core from Vivado 2015.1 to 2015.2 and the BUFG_GT is no longer locked down.

This appears to be the root cause of the issue.

The recommendation is to review the 2015.1 BUFG_GT locations and use them in 2015.2.

Please note that in general, we do NOT recommend locking down BUFG_GT in UltraScale - this is a temporary work-around for this issue.

Please note that the BUFG_GT LOCs are in the IP .xdc file, but they are commented out in order to provide more flexibility to the placer in the 2015.2 release.

Another option to address this would be to copy those xdc constraints into a top level .xdc file (along with the correct full path of the BUFG_GT) to ensure that the LOCs are fixed.

AR# 65044
Date Created 07/22/2015
Last Updated 08/11/2015
Status Active
Type Known Issues
  • Virtex UltraScale
  • Kintex UltraScale
  • Vivado Design Suite - 2015.2
  • PCI-Express (PCIe)