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AR# 65045

2015.2 Vivado Timing Closure - MIG Timing (IP version 7.0 and 7.1) - Known Issues Article


When users connect a significant amount of logic to the MIG user interface clock, timing violations (both setup and hold) can result due to large (> 1ns) clock skew.  This can occur between riu_clk and mmcm_clkout0 or simply on mmcm_clkout0 itself.  These results are typically seen on a placed but not yet routed netlist.


When users connect a significant amount of logic to the MIG user interface clock (mmcm_clkout0) and this logic gets placed several clock regions away from the MIG IP, it can create a scenario where the placer chooses a CLOCK_ROOT for the MIG clock that can cause significant skew or timing degradation.  When this scenario occurs, there are multiple ways to address it.  At a minimum, be aware of this issue and try to minimize the number of crossings between MIG logic and user logic.

1.  The user can floorplan the logic connected to the MIG user interface clock (mmcm_clkout0) to use the same clockregion rows that the MIG MMCM is placed in.  For example - if the MIG MMCM is placed in clock region X2Y12, the user logic could be floorplanned to clockregions X0Y12 to X4Y12.

2.  Another option is to lock the CLOCK ROOTs of the riu_clk and the mmcm_clkout0 to the same clock region where the MIG MMCM is placed.  This solution has the best chance for success when there is limited customer logic connected to the MIG user interface clock.

3.  The next option is to create a separate BUFG that will drive the user logic.  This BUFG will connect to the CLKOUT0 pin of the MIG MMCM just as the clocks mmcm_clkout0 and riu_clk do.  The end result is three BUFGCE_DIV in parallel.  One BUFGCE_DIV drives riu_clk, one BUFGCE_DIV drives the MIG logic, the other BUFGCE_DIV drives the user logic.  In this way, the tool can select distinct CLOCK ROOTs for the MIG logic and the user logic.  A tcl script called insertClockBuffer.tcl (attached to this AR) can be run after the opt_design phase to accomplish this goal.  Please carefully follow the instructions for using this script in order to ensure that a clock buffer is connected IN PARALLEL with the other MIG clocks.

Please see External Attachments of this article to get the insertClockBuffer.tcl script

a.  You will need to identify the hierarchical paths to the MMCM in each MIG core as well as the top level hierarchical path of each MIG core.

b.  Identify the net coming from the MIG MMCM CLKOUT0 pin:
set clock_source_net [get_nets -of [get_pins hierarchical_path_to_mig_mmcm/mmcme3_adv_inst/CLKOUT0]]

c.  Identify the net that is connected to the user interface clock at the top of the MIG hierarchy
set user_clock_net [get_nets -of [get_pins hierarchical_path_to_mig_top/*ui_clk]]

d.  Identify the clock region where the MIG MMCM is to be placed (For example Clock Region X2Y12)

e.  If using Vivado project - create post_opt.tcl script as below and be sure to add it to each implementation build as a post opt_design tcl script.  If using non-project flow, just use these lines AFTER the opt_design step.
set clock_source_net [get_nets -of [get_pins hierarchical_path_to_mig_mmcm/mmcme3_adv_inst/CLKOUT0]]
set user_clock_net [get_nets -of [get_pins hierarchical_path_to_mig_top/*ui_clk]]
source insertClockBuffer.tcl
insertClockBuffer $user_clock_net  BUFGCE_DIV $clock_source_net
set parallel_bufgs [get_cells -of [get_pins -leaf -filter {DIRECTION==IN} -of $clock_source_net]]
set parallel_bufg_nets [get_nets -of [get_pins -filter {DIRECTION==OUT} -of $parallel_bufgs]]
set_property CLOCK_ROOT XXYY $parallel_bufg_nets

f.  Verify that the script actually created a buffer in parallel by opening the optimized checkpoint and looking for the extra buffer connected to the CLKOUT0 pin of the MMCM

4.  If desired, the CLOCK_ROOT properties of the 3 BUFGCE_DIV in option #3can be locked down to the same clock region using the Tcl below.  This technique can help reduce skew between the user logic and the MIG logic.
set parallel_bufgs [get_cells -of [get_pins -leaf -filter {DIRECTION==IN} -of $clock_source_net]]
set parallel_bufg_nets [get_nets -of [get_pins -filter {DIRECTION==OUT} -of $parallel_bufgs]]
set_property CLOCK_ROOT XXYY $parallel_bufg_nets


Associated Attachments

Name File Size File Type
insertClockBuffer.tcl 4 KB TCL
AR# 65045
Date 08/20/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2014.4
  • MIG
  • MIG UltraScale
  • Memory Interface and Controller
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