Version Found: MIG v7.1
Version Resolved: See (Xilinx Answer 58435)
When CAS Latency (CL) is set to 17 for DDR4 UltraScale IP, the design will fail during calibration with DQS Gate calibration errors.
The error message is similar to the following:
CL=17 support has been recently added through the JEDEC JES79-4A standard.
CL=17 will be supported in a future release of DDR4 UltraScale.
Until this time, please use either 16 or 18, whichever is supported by the memory vendor.
07/23/2015 - Initial Release