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AR# 65060

Vivado 2015.1 - No insertion of BUFG_GT_SYNC on BUFG_GT resulting in unrouted net

Description

For a design that includes an Interlaken core, the router fails to complete.
 

CRITICAL WARNING: [Route 35-54] Net: u_interlaken/U0/gen_ultrascale_ilkn.inst_ILKN/interlaken_0_gt_i/inst/gen_gtwizard_gthe3_top.interlaken_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[2].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/interlaken_gtwiz_userclk_rx_reset_in is not completely routed.
Resolution: Run report_route_status for more information.

CRITICAL WARNING: [Route 35-54] Net: u_interlaken/U0/gen_ultrascale_ilkn.inst_ILKN/interlaken_0_gt_i/inst/gen_gtwizard_gthe3_top.interlaken_0_gt_gtwizard_gthe3_inst/gen_gtwizard_gthe3.gen_channel_container[3].gen_enabled_channel.gthe3_channel_wrapper_inst/channel_inst/interlaken_gtwiz_userclk_tx_reset_in is not completely routed.
Resolution: Run report_route_status for more information.

CRITICAL WARNING: [Route 35-7] Design has 4 unroutable pins, potentially caused by placement issues.


 

The nets in question are reset signals that drive BUFG_GTs.

Solution

Generally, opt_design will insert a BUFG_GT_SYNC primitive onto the associated BUFG_GTs and the BUFG_GT_SYNC is used to drive BUFG_GTs.

In this case, the nets specified fail to route because the BUFG_GTs driven by the nets are not being driven by a BUFG_GT_SYNC primitive.

opt_design is unable to insert a BUFG_GT_SYNC due to DONT_TOUCH properties on the underlying GT Wizard IP interfaces.

 

You can use one of the following work-arounds.

  • Set DONT_TOUCH as FALSE for the associated IP interfaces in the top level XDC
  • Manually instantiate BUFG_GT_SYNC in HDL
AR# 65060
Date Created 07/24/2015
Last Updated 07/31/2015
Status Active
Type General Article
Devices
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2