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AR# 65074

AXI Bridge for PCIe Gen3 (Vivado 2015.2) - TSK_TX_MEMORY_WRITE_32 uses incorrect value of tkeep

Description

Version Found: v1.1 (Rev1)

Version Resolved and other Known Issues: See (Xilinx Answer 61898)

The Root Port (RP) model in the AXI Bridge for PCIe Gen3 example design does not send a Memory Write request packet correctly, because RP is set to address-aligned mode and the value of s_axis_rq_tkeep is fixed.

Solution

This is a known issue to be fixed in the next release of the core.

Please modify "pcie_exp_usrapp_tx.v" as shown below to fix the issue in the current release.

At line 1355:

Original:

                          1 : begin len_i_c = len_i_c - 1;  end  // D0---------
                          2 : begin len_i_c = len_i_c - 2;  end  // D0-D1--------
                          3 : begin len_i_c = len_i_c - 3;  end  // D0-D1-D2-------
                          4 : begin len_i_c = len_i_c - 4;  end  // D0-D1-D2-D3------
                          5 : begin len_i_c = len_i_c - 5;  end  // D0-D1-D2-D3-D4-----
                          6 : begin len_i_c = len_i_c - 6;  end  // D0-D1-D2-D3-D4-D5--
                          7 : begin len_i_c = len_i_c - 7;  end  // D0-D1-D2-D3-D4-D5-D6
                          0 : begin len_i_c = len_i_c - 8;  end  // D0-D1-D2-D3-D4-D5-D6-D7----

Change to the following:

                          1 : begin len_i_c = len_i_c - 1; s_axis_rq_tkeep <= #(Tcq) 8'h01; end  // D0---------
                          2 : begin len_i_c = len_i_c - 2; s_axis_rq_tkeep <= #(Tcq) 8'h03; end  // D0-D1--------
                          3 : begin len_i_c = len_i_c - 3; s_axis_rq_tkeep <= #(Tcq) 8'h07; end  // D0-D1-D2-------
                          4 : begin len_i_c = len_i_c - 4; s_axis_rq_tkeep <= #(Tcq) 8'h0F; end  // D0-D1-D2-D3------
                          5 : begin len_i_c = len_i_c - 5; s_axis_rq_tkeep <= #(Tcq) 8'h1F; end  // D0-D1-D2-D3-D4-----
                          6 : begin len_i_c = len_i_c - 6; s_axis_rq_tkeep <= #(Tcq) 8'h3F; end  // D0-D1-D2-D3-D4-D5--
                          7 : begin len_i_c = len_i_c - 7; s_axis_rq_tkeep <= #(Tcq) 8'h7F; end  // D0-D1-D2-D3-D4-D5-D6
                          0 : begin len_i_c = len_i_c - 8; s_axis_rq_tkeep <= #(Tcq) 8'hFF; end  // D0-D1-D2-D3-D4-D5-D6-D7----


At line 1365:

Original:

      len_i_c = len_i_c - 8;

Change to the following:

      begin len_i_c = len_i_c - 8; s_axis_rq_tkeep <= #(Tcq) 8'hFF; end

Note: "Version Found" refers to the version where the problem was first discovered.

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History:

08/19/2015 - Initial Release

AR# 65074
Date Created 07/27/2015
Last Updated 08/26/2015
Status Active
Type Known Issues
IP
  • AXI PCIe Gen3