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AR# 65077

2015.2 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2015.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2015 Xilinx, Inc. All rights reserved.

This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws.

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and

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100G Ethernet (1.6)

* Version 1.6

* Example Design Code Optimization

* AXI4 Lite User Interface for Simplex TX/RX

10G Ethernet MAC (15.0)

* Version 15.0 (Rev. 1)

* Fixed incorrect mapping of PFC refresh values when configuration vector is used

* Fixed incorrect use of s_axi_rvalid in unmapped AXI-Lite address space (0x320-0x3FC)

* Fixed Enhanced VLAN RX where Length field position can affect truncation

* Fixed Stacked VLAN RX issue where frames with more than 4 VLAN headers can be incorrectly received

* Fixed corner case TX issue - frame just oversize and no tlast signaled on AXI4 Stream

* Fixed corner case TX issue - short frame (16-20 bytes) can corrupt custom preamble for following frame

* Fixed TX issue - short frame (16-20 bytes) with no deassertion of tx_axis_tvalid can affect previous frames terminate

* Limit user programmable IFG value to a maximum of 0xFC (1008 bytes)

* Changed AXI4-Lite address decode logic for Statistics registers to avoid a race condition in IES behavioral simulations

* Improved accuracy of the TX bytes valid statistics vector bits

* Update 64 bit example design FIFO to correctly respond to TREADY after TLAST

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 1)

* Allow Autonegotiation FSMs to be recognized correctly by tools

* Update to 7 Series GTHE2 transceiver parameters

* Added synchronizer on pcs_loopback bit of configuration_vector for 32bit cores

* Added presets to all Example Design top level registers

* Fixed 2x-too-long wait timers in training block for UltraScale devices

* Updated the sim_speedup_control logic to ensure that the correct timer values can always be obtained in the final bitstream

10G Ethernet Subsystem (3.0)

* Version 3.0 (Rev. 1)

* Updated the default value of the 1588 Transmitted Timestamp Adjustment Control Register for GTYE3 permutations

* Updated the default value of the 1588 RX Fixed Latency MDIO register for GTYE3 permutations

* Allow 10GBASE-KR Autonegotiation FSMs to be recognized correctly by tools

* Update to 7Series GTHE2 transceiver parameters

* Added synchronizer on PCS loopback bit of configuration_vector for 32bit cores

* Fixed 2x-too-long wait timers in the 10GBASE-KR training block for UltraScale devices

* Updated the sim_speedup_control logic to ensure that the correct timer values can always be obtained in the final bitstream

* Fixed incorrect mapping of PFC refresh values when configuration vector is used

* Fixed incorrect use of s_axi_rvalid in unmapped AXI-Lite address space (0x320-0x3FC)

* Fixed Stacked VLAN RX issue where frames with more than 4 VLAN headers can be incorrectly received

* Fixed corner case TX issue - frame just oversize and no tlast signaled on AXI4 Stream

* Fixed corner case TX issue - short frame (16-20 bytes) can corrupt custom preamble for following frame

* Limit user programmable IFG value to a maximum of 0xFC (1008 bytes)

* Changed AXI4-Lite address decode logic for Statistics registers to avoid a race condition in IES behavioral simulations

* Improved accuracy of the TX bytes valid statistics vector bits

* Update 64 bit example design FIFO to correctly respond to TREADY after TLAST

1G/2.5G Ethernet PCS/PMA or SGMII (15.0)

* Version 15.0 (Rev. 1)

* Default Insertion Loss at Nyquist value of transceiver configuration preset changed to result in better default RX equalization settings for Gigabit-Ethernet preset; now using LPM rather than DFE

* Correcting default value of txdiffctrl to "1000" for vhdl

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 6)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 8)

* No changes

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 8)

* No changes

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 7)

* No changes

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 8)

* No changes

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 7)

* No changes

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 7)

* No changes

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 6)

* No changes

7 Series FPGAs Transceivers Wizard (3.5)

* Version 3.5 (Rev. 1)

* Added support for XQ7Z045RFG676, XQ7Z100RF1156 and XQ7VX690TRF1158 devices

* Updated the GTZ design to release the resets of individual lanes one after another starting from master lane.

7 Series Integrated Block for PCI Express (3.1)

* Version 3.1 (Rev. 1)

* Fixed GTP DRP write issue - (Xilinx Answer 62770)

* Added support for xq7z100 device

* Added support for Post Synthesis/Implementation netlist simulation for EP/Verilog mode, for non-PIPE mode only

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 3)

* No changes

AXI 1G/2.5G Ethernet Subsystem (7.0)

* Version 7.0 (Rev. 1)

* For UltraScale devices in GMII/RGMII - Updated the Reset circuit to IDELAYCTRL to not have dependency on RDY output.

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 3)

* No changes

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 3)

* No changes

AXI BFM Cores (5.0)

* Version 5.0 (Rev. 6)

* GUI related updates

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 4)

* No changes

AXI Bridge for PCI Express Gen3 Subsystem (1.1)

* Version 1.1 (Rev. 1)

* Added Clock interface for the signal ext_ch_gt_drpclk

* Fixed issue with the location constraints for refclk_ibuf for xcvu095-ffvc2104, xcvu125-flvc2104 and xcvu190-flga2577

* Added MSIX Interface at the core boundary

* Added support for xq7vx690t-rf1158 device and package

* Fixed issue with outgoing packet's Tag management

AXI CAN (5.0)

* Version 5.0 (Rev. 8)

* No changes

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 5)

* No changes

AXI Chip2Chip Bridge (4.2)

* Version 4.2 (Rev. 5)

* GUI related updates

* Example design minor updates, no functional changes

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 4)

* No changes

AXI Crossbar (2.1)

* Version 2.1 (Rev. 6)

* No changes

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 4)

* No changes

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 5)

* No changes

AXI DataMover (5.1)

* Version 5.1 (Rev. 7)

* Change done to enable device support. No functional change.

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 6)

* Minor changes in Example Design for Enhanced support, No functional changes

AXI EMC (3.0)

* Version 3.0 (Rev. 5)

* Constraints updates for memory interface signals, no functional changes

* DRC added in bd to ensure axi clock and rdclk are connected from same source, no functional changes

AXI EPC (2.0)

* Version 2.0 (Rev. 8)

* Minor updates to example design, No functional changes

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 1)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 3)

* No changes

AXI GPIO (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI HWICAP (3.0)

* Version 3.0 (Rev. 9)

* Enhanced support for UltraScale plus devices. No functional changes.

AXI IIC (2.0)

* Version 2.0 (Rev. 8)

* No changes

AXI Interconnect (2.1)

* Version 2.1 (Rev. 6)

* No changes

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 4)

* Corrected help text in customization dialog

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 2)

* No changes

AXI MMU (2.1)

* Version 2.1 (Rev. 3)

* No changes

AXI Master Burst (2.0)

* Version 2.0 (Rev. 6)

* No changes

AXI Memory Mapped To PCI Express (2.6)

* Version 2.6 (Rev. 1)

* Added an option to hide RP BAR to prevent CPU from unnecessarily enumerating large RP BAR

* Added an option to have 4GB RP BAR size (Address Translation will not be performed if 4GB BAR is used)

* Added support to handle empty S-AXI data beat at the beginning of PCIe transaction

* Fixed back-to-back AXI Lite transaction lock up

* Fixed s_axi_ctl_wstrb use case for AXI Lite transaction towards PCIe bridge

* Fixed parameter propagation for ext_ch_gt_drpclk port in IPI

* Added support for xq7z100 device

* Added synthesizable RP example design

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 4)

* No changes

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 7)

* GUI related updates

AXI Protocol Checker (1.1)

* Version 1.1 (Rev. 6)

* No changes

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 5)

* No changes

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 4)

* GUI related updates

AXI Register Slice (2.1)

* Version 2.1 (Rev. 5)

* No changes

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 9)

* Minor GUI Updates

AXI Timebase Watchdog Timer (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Timer (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI Traffic Generator (2.0)

* Version 2.0 (Rev. 6)

* No changes

AXI UART16550 (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 6)

* No changes

AXI Uartlite (2.0)

* Version 2.0 (Rev. 9)

* Minor updates to example design. No functional changes.

AXI Video Direct Memory Access (6.2)

* Version 6.2 (Rev. 4)

* Change done to enable device support. No functional change.

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 7)

* No changes

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 2)

* No changes

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 4)

* changes to improve internal automation, no functional changes.

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 5)

* No changes

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 6)

* No changes

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 4)

* No changes

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 6)

* No changes

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 4)

* No changes

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 6)

* Update IP integrator automation to improve conflict resolution. No functional changes.

AXI4-Stream Protocol Checker (1.1)

* Version 1.1 (Rev. 5)

* No changes

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 5)

* No changes

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 5)

* No changes

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 5)

* No changes

AXI4-Stream to Video Out (3.0)

* Version 3.0 (Rev. 7)

* No changes

Accumulator (12.0)

* Version 12.0 (Rev. 6)

* No changes

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 6)

* No changes

Aurora 64B66B (10.0)

* Version 10.0 (Rev. 1)

* Added support for XQ7Z045RFG676, XQ7Z100RF1156 and XQ7VX690TRF1158 devices

Aurora 8B10B (11.0)

* Version 11.0 (Rev. 1)

* Added support for XQ7VX690T, XQ7Z045 and XQ7Z100 devices

* BUFG removed on DRP Clock input

* TXPMARESETDONE used in rxstartupfsm for GTP RX-onlySimplex configuration

* set_false_path constrain on synchronizers updated

Binary Counter (12.0)

* Version 12.0 (Rev. 6)

* No changes

Block Memory Generator (8.2)

* Version 8.2 (Rev. 6)

* Internal device family change, no functional changes

CIC Compiler (4.0)

* Version 4.0 (Rev. 7)

* No changes

CORDIC (6.0)

* Version 6.0 (Rev. 7)

* No changes

CPRI (8.4)

* Version 8.4 (Rev. 1)

* Output port clk_316_out was added.

* Added default values for all clock input ports in IPI.

* Added support for the xq7z100 device.

* Conflict between barrel shift and speed change DRP accesses resolved.

* Corrected routing into DRP arbiter in UltraScale devices.

* GUI changes for -1 speed grade parts.

Chroma Resampler (4.0)

* Version 4.0 (Rev. 6)

* No changes

Clocking Wizard (5.1)

* Version 5.1 (Rev. 7)

* Internal device family change, no functional changes

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 7)

* No changes

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 6)

* No changes

Complex Multiplier (6.0)

* Version 6.0 (Rev. 8)

* Corrected output pipeline widths for some DSP48 multiplier configurations targeting UltraScale devices.

Convolution Encoder (9.0)

* Version 9.0 (Rev. 7)

* No changes

DDS Compiler (6.0)

* Version 6.0 (Rev. 9)

* Addition of MEX wrapper

DSP48 Macro (3.0)

* Version 3.0 (Rev. 9)

* Correction to "0" instruction validation.

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 7)

* No changes

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 8)

* Re-phrased internal function to avoid Vivado Simulator elaboration error. No functional changes.

DisplayPort (6.0)

* Version 6.0 (Rev. 1)

* Fixed US TX reset connectivity issue

* Removed redundant XDC which is covered as part of synchronizer cell in DP RX

* Fixed GT DRP host access issue in TX and RX.

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 8)

* No changes

Divider Generator (5.1)

* Version 5.1 (Rev. 7)

* Addition of MEX wrapper demonstration file.

ECC (2.0)

* Version 2.0 (Rev. 8)

* No changes

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 7)

* No changes

FIFO Generator (12.0)

* Version 12.0 (Rev. 4)

* No changes

FIR Compiler (7.2)

* Version 7.2 (Rev. 3)

* Correction to the GUI reported startup latency for polyphase interpolation configurations.

* Correction for Halfband Decimation with Symmetric rounding on UltraScale parts.

* Correction for Polyphase Interpolation with Convergent rounding where multiple DSP columns are required to support the data and/or coefficient width.

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 7)

* No changes

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 5)

* No changes

Floating-point (7.0)

* Version 7.0 (Rev. 9)

* Fixed latency allocation bug in double-precision natural logarithm operator affecting UltraScale devices only. Fully-pipelined latency consequently increases from 63 to 64 cycles.

* Added Half Precision option to GUI. This is Ease-of-Use only as Custom widths already allow this. No functional changes.

* Added default values to some signals to allow correct simulation with Synopsys VCS. No functional changes.

G.709 FEC Encoder/Decoder (2.2)

* Version 2.2

* Add option to use OTN Framer interface

* Bugfix for invalid DSTS TVALID de-assertion in OTU4 configurations when TREADY was de-asserted around TVALID rising edge

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Bugfix for OTU1 statistics reference design LFSR seed. LFSR was stuck at zero.

* Bugfix for statistics reference design scrambler reset. Output qualifying signal pipelines were not flushed.

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 9)

* Supported devices and production status are now determined automatically, to simplify support for future devices

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 9)

* Supported devices and production status are now determined automatically, to simplify support for future devices

Gamma Correction (7.0)

* Version 7.0 (Rev. 7)

* No changes

Gmii to Rgmii (4.0)

* Version 4.0

* No changes

High Speed SelectIO Wizard (1.1)

* Version 1.1 (Rev. 3)

* Conditions for ports appearing in template files are updated in coreinfo.yml

* In serial mode SELF_CALIBARATE is Enabled, and delay format is always set to time

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 9)

* Updated CFG values of GT above linerate 11Gbps.

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 8)

* No changes

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 9)

* Fixed issue of REFCLK selection getting set to default if refclk order is changed from bottom to top.

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 7)

* Updated Product Guide URL

IBERT UltraScale GTH (1.2)

* Version 1.2 (Rev. 1)

* Added XSDB reg to reset lutram FIFO.

IBERT UltraScale GTY (1.1)

* Version 1.1 (Rev. 1)

* Added XSDB reg to reset lutram FIFO.

IEEE 802.3bj RS-FEC (1.0)

* Version 1.0 (Rev. 1)

* Timing improvements to core and reduction in LUT count

ILA (Integrated Logic Analyzer) (5.1)

* Version 5.1 (Rev. 1)

* Updated IP XDC constraints to fix Partial False path scenario in ILA when operated in mulit-clock domain

* Updated IP XDC constraints to fix critical warnings in High Speed Design Debugging mode

IOModule (3.0)

* Version 3.0 (Rev. 2)

* Use common preset implementation for board interfaces, no functional changes

Image Enhancement (8.0)

* Version 8.0 (Rev. 7)

* No changes

Interlaken (1.6)

* Version 1.6

* Example design Code optimization

* 3.125G lane rate support for all the lanes from 1 to 12

* DISABLE SKIP WORD and BYPASS MODE options added in GUI Tab-I

* Rate Limiter GUI option enabled in GUI Tab-2

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 6)

* No changes

JESD204 (6.1)

* Version 6.1 (Rev. 2)

* Fixed issue in receive JESD204 where a SYNC~ de-assertion for less than 5 frames plus 9 octets could cause a link initialization

* Fixed issue with SYNC being held low for an extra frame when Error Reporting via SYNC was enabled

* AXI-Streaming buses are now associated with tx/rx core clock and not tx/rx aclk

JESD204 PHY (2.0)

* Version 2.0 (Rev. 1)

* Removed redundant cpll reset logic for 7 Series. This input was being ignored by the Transceiver. Controlled by internal state machines.

* Added logic to create a reset pulse if PLL LOCK is lost. 7-Series only

* Fixed issue with CPLLPD and QPLLPD default values when AXI4-Lite Management Interface is enabled. PLLs are powered down if not enabled.

JTAG to AXI Master (1.0)

* Version 1.0 (Rev. 8)

* Code clean-up to improve coverage numbers

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 6)

* No changes

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 7)

* No changes

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 8)

* Rephrased RTL to ensure correct simulation with Cadence IES 14.10.011. No functional changes.

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 7)

* No changes

LTE RACH Detector (2.0)

* Version 2.0 (Rev. 7)

* No changes

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 7)

* No changes

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 6)

* No changes

Mailbox (2.1)

* Version 2.1 (Rev. 4)

* Corrected help text in customization dialog

Memory Interface Generator (MIG 7 Series) (2.3)

* Version 2.3 (Rev. 2)

* Added Address Mirroring support for DDR3 Dual Rank UDIMMs.

* Resolved DDR3 AXI, ECC enabled design failures. See (Xilinx Answer 64421) for details.

Memory Interface Generator (MIG) (7.1)

* Version 7.1

* Updated Version 7.1

MicroBlaze (9.5)

* Version 9.5 (Rev. 1)

* Prevent instruction cache stream from fetching an incorrect cache line, occurring in rare cases with many outstanding read accesses. Versions that have this issue: 9.0, 9.1, 9.2, 9.3, 9.4, 9.5. Can only occur when instruction cache stream is enabled.

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 3)

* Added constraints for BSCAN output signals

MicroBlaze MCS (2.3)

* Version 2.3 (Rev. 1)

* Added constraints for BSCAN output signals

Multiplier (12.0)

* Version 12.0 (Rev. 8)

* Rephrased RTL to work around issue when simulating with Cadence IES. No functional changes.

* Corrected output pipeline widths for some DSP48 multiplier configurations targeting UltraScale devices.

Multiply Adder (3.0)

* Version 3.0 (Rev. 6)

* No changes

Mutex (2.1)

* Version 2.1 (Rev. 4)

* Corrected help text in customization dialog

Partial Reconfiguration Controller (1.0)

* Version 1.0

* No changes

Peak Cancellation Crest Factor Reduction (6.0)

* Version 6.0 (Rev. 1)

* Fixes for core re-customization issue

Processor System Reset (5.0)

* Version 5.0 (Rev. 7)

* No changes

QSGMII (3.3)

* Version 3.3 (Rev. 1)

* Default Insertion Loss at Nyquist value of transceiver configuration preset changed to result in better default RX equalization settings for QSGMII preset; now using LPM rather than DFE

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 6)

* No changes

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 5)

* No changes

RXAUI (4.3)

* Version 4.3 (Rev. 1)

* For UltraScale transceivers, an update in attributes results in a change in mode of the Rx Equalizer from DFE to LPM.

* Added initial values to HDL registers to prevent X propagation in behavioral simulations

* Added support for xq7z100rf1156-1I devices

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 8)

* No changes

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 7)

* No changes

S/PDIF (2.0)

* Version 2.0 (Rev. 8)

* No changes

SMPTE 2022-1/2 Video over IP Receiver (2.0)

* Version 2.0 (Rev. 2)

* No changes

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

* Version 2.0 (Rev. 2)

* No changes

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 5)

* removed Zynq speed grade -1 devices with Artix-7 fabric, from the supported family list

SMPTE UHD-SDI (1.0)

* Version 1.0

* No changes

SMPTE2022-5/6 Video over IP Receiver (5.0)

* Version 5.0 (Rev. 1)

* Enhanced mem_wr_ctrl to handle MOT support for write transaction

* Fixed FEC packets got scanned for missing packets before recovered packets are updated

* Add null packet insertion at output for missing packets

* Fixed handshake synchronization between channelizer and sdi_reformatter

SMPTE2022-5/6 Video over IP Transmitter (4.0)

* Version 4.0 (Rev. 3)

* Removed FIFO_GEN subcore as it is not used in the core

SPI-4.2 (13.0)

* Version 13.0 (Rev. 6)

* No changes

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 5)

* No changes

Serial RapidIO Gen2 (4.0)

* Version 4.0

* Removed Generate Physical Layer Only option. Generates Full Design by default

* Updated the SIDE_BAND_SIGNALS and CORE_DEBUG interfaces with correct interface association (Master)

* Upgraded to major version for single licensing

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 4)

* No changes

System Cache (3.1)

* Version 3.1 (Rev. 1)

* Improved automatic assignment of address parameters to handle up to 64-bit addresses

* Corrected DRC checking and assignment of AXI interface data widths

* Allow different cache line lengths on optimized ports

System Management Wizard (1.2)

* Version 1.2 (Rev. 1)

* GUI Related Updates. No Functional Changes.

Test Pattern Generator (6.0)

* Version 6.0 (Rev. 4)

* No changes

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 2)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 1)

* For UltraScale devices in GMII/RGMII - Updated the Reset circuit to IDELAYCTRL to not have dependency on RDY output.

* Updated the Example design XDC file, for non-internal modes, to add a set_false_path constraint to input of synchronizer module.

UltraScale FPGAs Transceivers Wizard (1.5)

* Version 1.5 (Rev. 2)

* Improved performance of GTY transceivers via parameter updates

* Updated GTH transceiver parameters to enable QPLL temperature compensation, and for QPLL bandwidth tuning to address TX to QPLL coupling issue when feedback divider value exceeds 80

* Addressed an issue that caused the reset controller helper block to issue unreliable CPLL resets, by extending the CPLLPD pulse width to 2us

* Updated the default Insertion Loss at Nyquist value of several transceiver configuration presets, resulting in better default RX equalization settings for those presets, in many cases using LPM rather than DFE

* Expanded the range of the PPM offset between receiver and transmitter option in the Wizard customization GUI to match published UltraScale Architecture Data Sheet values

UltraScale Soft Error Mitigation (2.0)

* Version 2.0 (Rev. 2)

* No changes

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.0)

* Version 4.0 (Rev. 1)

* Added support for x8Gen3 configuration for all -1 speed grades

* Added Tandem and PR over PCIe support for ku035 and vu440 devices

* Adjusted STARTUP I/O port widths

* Fixed issue with the location constraints for refclk_bufi for xcvu095-ffvc2104,xcvu190-flga2577 and xcvu125-flvc2104

* Fixed link train failure during cold reboot (Xilinx Answer Record - 64404)

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 8)

* Updated to avoid control set optimization for 1 bit probes

Video Deinterlacer (4.0)

* Version 4.0 (Rev. 8)

* No changes

Video In to AXI4-Stream (3.0)

* Version 3.0 (Rev. 7)

* No changes

Video On Screen Display (6.0)

* Version 6.0 (Rev. 8)

* No changes

Video Scaler (8.1)

* Version 8.1 (Rev. 5)

* No changes

Video Timing Controller (6.1)

* Version 6.1 (Rev. 5)

* No changes

Video over IP FEC Receiver (1.0)

* Version 1.0

* No changes

Video over IP FEC Transmitter (1.0)

* Version 1.0 (Rev. 1)

* Updated to remove the issue of memory collision on RAM

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.0)

* Version 4.0 (Rev. 1)

* Removed EP model user application files from the synthesis list of RP configuration example design

* Added support for xq7vx690t-rf1158

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 3)

* Internal code rephrasing to allow correct behavioral simulation using VCS

XADC Wizard (3.1)

* Version 3.1

* Corrected the Alarm limits for VCCINT and VCCBRAM for -2L speedgrade devices.

XAUI (12.2)

* Version 12.2 (Rev. 1)

* For UltraScale transceivers, an update of attributes results in a change in mode of the Rx Equalizer from DFE to LPM.

* Revised 20Gbps device support, including enabling support for ffv and fbv packages in 7 Series devices in supported speed grades

* Added support for xq7z100rf1156-1I devices

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 5)

* No changes

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 1)

* No changes

ZYNQ7 Processing System BFM (2.0)

* Version 2.0 (Rev. 4)

* Bug fixes done

axi_sg (4.1)

* Version 4.1 (Rev. 1)

* No changes

interrupt_controller (3.1)

* Version 3.1 (Rev. 1)

* No changes

lib_bmg (1.0)

* Version 1.0 (Rev. 1)

* No changes

lib_cdc (1.0)

* Version 1.0 (Rev. 1)

* No changes

lib_fifo (1.0)

* Version 1.0 (Rev. 2)

* Enhanced support for UltraScale plus devices

lib_pkg (1.0)

* Version 1.0 (Rev. 1)

* No changes

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 1)

* No changes


AR# 65077
Date Created 07/28/2015
Last Updated 10/01/2015
Status Active
Type Release Notes
Tools
  • Vivado Design Suite - 2015.2