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AR# 65110

Zynq-7000 AP SoC: PS and PL eFUSE summary and correlation with Xilinx Documents

Description

This Article summarizes the PS and PL eFUSE settings, and clarifies the naming convention of Xilinx Documentation (UG585, UG470) and Xilinx Tools (LibXil SKey described in UG1191 and Vivado Device Programmer).

Solution

Please find the tables below:

 

 

 

 

 

 

 

UG585 (PL eFUSE) UG470 (FUSE_CNTL) Bit Position Functionality Vivado Programmability
(Starting from 2015.2)

Impact Programmability

UG1191 (LibXil SKey Programmability)
XSK_EFUSEPL_FORCE_USE_AES_ONLY Zynq-7000 only.
NOT documented in (UG470).
8 Must boot securely and use the eFUSE key as the AES key source. Non-secure boot of the device is not allowed. Yes
Register bit name:
eFUSE_Secure_Boot
Yes (14.7) Register bit name:
eFUSE Secure Boot
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_FORCE_USE_AES_ONLY
XSK_EFUSEPL_BBRAM_KEY_DISABLE Zynq-7000 only.
NOT documented in (UG470).
10 If boot in secure mode must use eFUSE key as the AES key source (not BBRAM). Non-secure boot is allowed. Yes
Register bit name:
BBRAM_Key_Disable
Yes (14.7) Register bit name:
BBRAM Key Disable
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_BBRAM_KEY_DISABLE
XSK_EFUSEPL_DISABLE_JTAG_CHAIN Zynq-7000 only.
NOT documented in (UG470).
9 DAP and TAP permanently disabled. Yes (command line)
Command:
program_hw_devices
control_efuse {0200}
Yes (14.7) Register bit name:
JTAG Chain Disable
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_DISABLE_JTAG_CHAIN(alias) XSK_BBRAM_DISABLE_JTAG_CHAIN
  AES_Exclusive 1 Part has to be power-cycled to be reconfigured. Disables partial reconfiguration from external configuration interfaces. Yes
Register bit name:
AES_Exclusive
Yes (14.7) Register bit name:
Configure After Power Cyle Only
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_FORCE_PCYCLE_RECONFIG
(alias)XSK_BBRAM_FORCE_PCYCLE_RECONFIG
  W_EN_B_Key_User 2 Disables programming of FUSE_AES (AES key) and FUSE_USER. Yes
Register bit name:
W_EN_B_Key_User
Yes (14.7) Register bit name:
Disable Write: Encryption Key Register(alias) User Register
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_DISABLE_KEY_WRITE
  R_EN_B_Key 3 Disables programming of FUSE_AES (AES key) and FUSE_USER. Disables reads of FUSE_AES. Yes
Register bit name:
R_EN_B_Key
Yes (14.7) Register bit name:
Disable Read: Encryption Key Register
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_DISABLE_AES_KEY_READ
  R_EN_B_User 4 Disables programming of FUSE_AES (AES key) and FUSE_USER. Disables reads of FUSE_USER.
This does not disable reading the user code through the EFUSE_USR component, although it disables reading the user code through the JTAG port.
Yes
Register bit name:
R_EN_B_User
Yes (14.7) Register bit name:
Disable Read: User Register
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_DISABLE_USER_KEY_READ
  W_EN_B_Cntl 5 Disables programming of control bits "FUSE_CNTL" as listed in this table. Yes
Register bit name:
W_EN_B_Cntl
Yes (14.7) Register bit name:
Disable Write: Control Register
Yes. To write the PL eFUSE using the driver, an external MUX on the board is required.
User-configurable parameter name:
XSK_EFUSEPL_DISABLE_FUSE_CNTRL_WRITE
  CFG_AES_Only 0 NOT applicable for Zynq-7000. Use Bit 8 instead. NA NA NA
  Reserved 6,7,11,
12,13
Reserved NA NA NA



UG585 (PS eFUSE) UG470 (FUSE_CNTL) Functionality Vivado Programmability Impact Programmability UG1191 (LibXil SKey user-configurable parameters)
eFuse Write Protection (2 fuses) Zynq-7000 only.
NOT documented in (UG470).
Prevents programming of the PS eFuse array only. No No Yes.
User-configurable parameter name:
XSK_EFUSEPS_ENABLE_WRITE_PROTECT
OCM ROM 128K CRC Enable Zynq-7000 only.
NOT documented in (UG470).
CRC of BootROM completed after POR. No No Yes.
User-configurable parameter name:
XSK_EFUSEPS_ENABLE_ROM_128K_CRC
RSA Authentication Enable Zynq-7000 only.
NOT documented in (UG470).
Forces BootROM to perform RSA authentication on unencrypted or encrypted files. No No Yes.
User-configurable parameter name:
XSK_EFUSEPS_ENALBE_RSA_AUTH
DFT JTAG Disable Zynq-7000 only.
NOT documented in (UG470).
DAP and TAP are disabled when booted in DFT mode. No No Yes.
User-configurable parameter name:
XSK_EFUSEPS_APB_DFT_JTAG_DISABLE
DFT Mode Disable Zynq-7000 only.
NOT documented in (UG470).
DFT boot mode is disabled. No No Yes.
User-configurable parameter name:
XSK_EFUSEPS_APB_DFT_MODE_DISABLE
AR# 65110
Date Created 07/30/2015
Last Updated 06/30/2016
Status Active
Type General Article
Devices
  • Zynq-7000