The HSYNC_WIDTH register (0x050) is documented in the DisplayPort Sink Core Configuration Space section of the DisplayPort Product Guide (PG064).
The default HSYNC_WIDTH is set to the max of 16 clocks.
The default configuration should cover most use cases, but if the user application requires, it can be reduced by updating the HSYNC_WIDTH register.
The DisplayPort core does not have a VSYNC_WIDTH register.
The VSYNC_WIDTH is fixed to 64 clocks.