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AR# 65154

LogiCORE IP DisplayPort - What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register?

Description

What is the HSYNC_WIDTH register and is there a related VSYNC_WIDTH register?

Solution

The HSYNC_WIDTH register (0x050) is documented in the DisplayPort Sink Core Configuration Space section of the DisplayPort Product Guide (PG064).

The default HSYNC_WIDTH is set to the max of 16 clocks.

The default configuration should cover most use cases, but if the user application requires, it can be reduced by updating the HSYNC_WIDTH register.

The DisplayPort core does not have a VSYNC_WIDTH register.

The VSYNC_WIDTH is fixed to 64 clocks.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54522 LogiCORE IP DisplayPort - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions N/A N/A
AR# 65154
Date Created 08/06/2015
Last Updated 08/07/2015
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • DisplayPort