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AR# 65167

2015.1: Block Design Tcl export fails to recreate project and gives validation Errors

Description

Sourcing a write_bd_tcl created script to re-create my project results in validation errors:

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'PCW QSPI PERIPHERAL ENABLE(PCW_QSPI_PERIPHERAL_ENABLE)' with value '1' for BD Cell '/Processor/processing_system7_0'. qspi mutex : Conflict from - and - ERROR: [IP_Flow 19-3478] Validation failed

What is the cause of this error?

Solution

This is a known issue in Vivado 2015.2 which will be fixed in later versions.

The issue occurs due to the dependency upon the order of the parameters being executed by the "set_property -dict [ list ...... ] " command.

To work around this issue, manually edit the Tcl file to set the QSPI properties first:

set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]

set_property -dict [ list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {0} CONFIG.PCW_QSPI_GRP_SS1_ENABLE {1} CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} ] $processing_system7_0

set_property -dict [ list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps} CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {100 Mbps} CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} CONFIG.PCW_I2C0_I2C0_IO {MIO 26 .. 27} CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} CONFIG.PCW_IRQ_F2P_INTR {1} CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {1} CONFIG.PCW_PJTAG_PJTAG_IO {MIO 22 .. 25} CONFIG.PCW_SD0_GRP_CD_ENABLE {1} CONFIG.PCW_SD0_GRP_CD_IO {MIO 46} CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {25} CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} CONFIG.PCW_SPI0_SPI0_IO {MIO 16 .. 21} CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {125} CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.217} CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.205} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.119} CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.146} CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {1}  ] $processing_system7_0

AR# 65167
Date Created 08/09/2015
Last Updated 08/10/2015
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite