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AR# 65176

Xilinx PCI Express - General Answer Records


This answer record provides a list of general PCI Express Answer Records that are not related to specific Xilinx PCI Express core only.

This article is part of the PCI Express Solution Centre
(Xilinx Answer 34536) - Xilinx Solution Center for PCI Express


Below is a list of answer records that are applicable to one or more Xilinx PCI Express cores. 

Most of the answer records below are for Virtex-5, Spartan-6 and Virtex-6 PCI Express cores, but some of them are generic and so apply to the latest cores too.

(Xilinx Answer 18329) What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?
(Xilinx Answer 19006) How many virtual channels do the Xilinx cores for PCI Express support?
(Xilinx Answer 33251) Application Note xapp859 Design Does Not Return Completion for Memory Requests with Non-zero Attribute Field
(Xilinx Answer 33918) Virtex-6, Spartan-6 FPGA and Block Plus Integrated Block Wrappers for PCI Express - Why is the root port model and testbench provided with the example simulation not passing Memory or I/O transactions to the user side interface?
(Xilinx Answer 34248) MSI interrupt is not received at the host
(Xilinx Answer 34777) Device not recognized by system
(Xilinx Answer 34800) Problems Associated with FPGA Configuration
(Xilinx Answer 34806) Software that Displays PCI Express Devices In System
(Xilinx Answer 34871) Using JTAG to Configure the Device
(Xilinx Answer 34873) Debugging System Recognition and Link Training Issues Using trn_lnk_up_n and trn_reset_n
(Xilinx Answer 35000) What happens if the power in the FPGA is re-configured, power is removed, or card removed during normal operation of the link
(Xilinx Answer 35033) Device is recognized by system, but problems occur
(Xilinx Answer 35034) Completion Timeouts Cause the System to Freeze
(Xilinx Answer 35412) Can Pinouts Be Changed?
(Xilinx Answer 35722) How to add a PCI Express cores to Project Navigator?
(Xilinx Answer 35748) Incorrect use of trn_trem_n could cause malformed TLPs to get transferred
(Xilinx Answer 35913) Why does a single memory read request result in multiple completions?
(Xilinx Answer 36049) TRN User Application Interface Questions
(Xilinx Answer 36063) Why is a NAK sent on a Previously ACKed Packet?
(Xilinx Answer 36137) trn_reset_n (user_reset_out for AXI) is deasserting, but trn_lnk_up_n (user_lnk_up_n for AXI) is not asserting
(Xilinx Answer 36207) Simulation Set-Up and Licensing Questions
(Xilinx Answer 36208) Simulation Questions Regarding Configuration Traffic
(Xilinx Answer 36215) Why does reading of BAR register return all zeroes?
(Xilinx Answer 36325) How to Disable ASPM?
(Xilinx Answer 36785) Supported Simulators
(Xilinx Answer 37007) Unsupported request bit not set when cfg_err_posted_n is deasserted and cfg_err_ur_n is asserted
(Xilinx Answer 37063) Are there any drivers available from Xilinx for PCI Express?
(Xilinx Answer 37180) How is the core configured to have Extended Tag Field Support?
(Xilinx Answer 37406) How to enumerate the endpoint when FPGA is configured after enumeration.
(Xilinx Answer 37472) How to read packets on the Integrated Block for PCI Express's memory (or MIM) interface
(Xilinx Answer 37497) What should the Target Link Speed register in the Link Control 2 Register be set to?
(Xilinx Answer 37517) Is it necessary to use only the recommended GTP/GTX locations in the User Guide?
(Xilinx Answer 37752) Issues in simulation when user inputs are perfectly aligned to trn_clk or user_clk_out
(Xilinx Answer 37817) How does a Gen 1 endpoint handle the reserved bits in the TS1/TS2 ordered sets that are used in Gen 2?
(Xilinx Answer 38064) What happens when there are multiple errors in a TLP
(Xilinx Answer 38430) Simulation Questions Regarding Link Training
(Xilinx Answer 38447) Memory reads result in 0xFFFFFFFF
(Xilinx Answer 38491) Where can documents be found that contain the performance numbers for Xilinx PCIe Integrated Block Cores? Article
(Xilinx Answer 38542) How to Calculate the Latency of a Packet Presented on the TRN Interface
(Xilinx Answer 38548) Simulation Traffic Questions
(Xilinx Answer 38552) Reasons for trn_tdst_rdy_n De-asserting Indefinitely
(Xilinx Answer 38988) How can I force a card to train to a smaller link width? How do I tape off lanes?
(Xilinx Answer 39380) Receiver detect problems
(Xilinx Answer 39720) Behavior of the configuration space after a reset to the core.
(Xilinx Answer 40310) What is a prefetchable bit?
(Xilinx Answer 41151) What happens if link has 8b10b errors?
AR# 65176
Date Created 08/10/2015
Last Updated 01/28/2016
Status Active
Type General Article
  • PCI-Express (PCIe)