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AR# 65196

Vivado IP Integrator - How to add an ELF to a Packaged Block Design

Description

I have a packaged Block Design (BD) that contains a MicroBlaze.

I would like to add my ELF to this BD.

How can I achieve this?

Solution


To achieve this, please follow the steps below for the Vivado version being used.

Vivado 2015.2:

Step 1: Create the MicroBlaze system that will eventually be packaged.

Step 2: Export to SDK, and create the ELF file.

Step 3: Associate the ELF file with the BD which will be packaged.

Keep note of the STC/STR properties. The STC (SCOPED_TO_CELLS) is the processor cell, the STR (SCOPED_TO_REF) is the module that contains the STC in the hierarchy.

This can be obtained by reading the ELF file properties in Vivado, after the ELF is Associated as shown below.

In the following example, the STC is set to microblaze_0, and the STR is set to mb_sys:

Step 4: Package the BD.

To do this, go to Tools -> Create and Package IP -> Select Package Block Design, and select your BD.

Next, you will see the path to place the IP:

Note: There is an issue in Vivado 2015.2 where the ELF is not copied over correctly.

To address this issue, copy the ELF file manually into the ip_repo folder (See previous screen capture).

Here you can create a data folder, and place the ELF into this folder within the ip_repo.


Next, in the File Group in the Packager GUI, select the Synthesis file group, and right click and add the ELF that you copied to the data folder in the ip_repo.

You can also add this to the Simulation folder.


Next, the STR/STC properties will need to be set in the ELF file.

To do this, highlight the ELF file, then in the IP file properties you can set the properties.

These can be set to the same properties that were used when associating the ELF (See step 3).


For example:



To finish, select Review and Package -> Package IP.

You can exit the Packager by selecting the "X"


Step 5: Test the IP.

You can now add the newly created IP to a new BD, and generate Output Products and the HDL Wrapper.


To verify that the ELF has been used during Synthesis, you can run Synthesis and then open the synthesized design.

In the opened Synthesized Design, select Edit -> Find and search for a PRIMITIVE_TYPE of BMEM.BRAM.

This will list all of the BRAMs in the system.

Find the BRAMs for the LMB BRAM (or the AXI BRAM if this is where the application was placed in the SDK) and select one of these BRAMs.

You can now check the cell properties.

Under CONFIG check the INIT_xx to verify that the contents are updated.


For example:



Vivado 2015.3:

In 2015.3, the steps above are not needed. 

However, there is a bug that needs to be worked around.

In order to getting this working, use the commands below from the Vivado TCL console:

  • ipx::open_core <path to IP>/component.xml
  • ipx::remove_all_cpu [ipx::current_core]
  • ipx::save_core

Note: to get the path to the IP repo, the TCL command below can be used:

  • get_property ip_repo_paths [current_project]

Next, refresh the IP catalog:

Next, click Update Selected to upgrade the IP:

Right Click on the BD, and Reset Output Products, and Generate Output Products.

Now, if the design is synthesized, then the BRAM init_strings should be initialized with the ELF data.

AR# 65196
Date Created 08/12/2015
Last Updated 10/15/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1