The 7 Series Xilinx Evaluation Boards have CKE pulled to ground with a 4.7 k resistor.
However the DDR3 Design Guidelines in (UG586) state:
"Address and control signals (A, BA, RAS_N, CAS_N, WE_N, CS_N, CKE, ODT)are to be terminated with the onboard DIMM termination.
If DIMM termination does not exist or a component is being used, a 40 pull-up to VTT at the far end of the line should be used (Figure 1-91). Except for the CK/CK_N which requires a differential termination as shown in Figure 1-93."
Which is correct?
The CKE pull-downs on our evaluation boards are incorrect.
This is error can be traced back to Virtex-6 MIG, where (UG406) incorrectly states that CKE should be pulled to ground with RESET.
This is a requirement for DDR2, not DDR3. See (Xilinx Answer 54844) for details.
We have contacted Micron regarding the issue and they have confirmed there is no harm in pulling CKE low during DDR3 initialization.
Please follow the Design Guidelines in (UG586) when designing a new PCB and terminate CKE to VTT with the rest of the address/control signals.