The reference clock takes time to propagate to the GTs PLL during FPGA configuration.
The reference clock AC coupling capacitor begins to charge up during configuration.
Depending on the configuration method, the capacitor may still be charging after configuration DONE.
This is more likely to occur with the faster programming methods such as PCAP (Zynq only) or BPI.
In the event that the GTX/GTH/GTP transceivers are released from reset before the reference clock has settled through the RC circuit, a second reset of the transceiver (C/QPLL+TX/RX) after the reference clock has settled is necessary.
Designs that have a free running clock from the SelectIO pins can implement a counter that counts 3 ms after configuration DONE to hold off releasing any GT resets.
Designs that do not have a free running clock can access cfgmclk via the STARTUPE2 primitive and assume its slowest frequency (65 MHz 50% = 32.5 MHz) to count 3ms after configuration DONE to hold off releasing any GT resets.
The 7 Series GT Wizard (specifically the reset FSM of the Wizard output) is updated for 2015.3 to allow the user to optionally enable an extra 3 ms delay before releasing resets.
For designs not yet in production release:
Select 10nF AC coupling capacitor instead of 100nF to decrease the charge up/settle time and update CPLL_INIT_CFG[9:0] and QPLL_INIT_CFG[9:0] to hex 3FF.
Impact to production designs:
This issue occurs during configuration or reference clock startup of the device.
A system that passed initial system testing will continue to pass in the field.
Some protocols have auto recovery mechanisms which would recover from any link up issues.
Depending on usage, some designs might already be allowing enough time for the reference clock to settle through the RC circuit.
For example, Upper layer or software controls issue a reset well after FPGA configuration is DONE.