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AR# 65212

Vivado Synthesis - MAX_FANOUT applied to IP internal net is not satisfied although replication does occur


The Fast Fourier Transform (FFT) IP has an internal high fanout CE signal, which makes timing closure challenging.

I am trying to disable the IPs OOC setting and set fanout as 100 for the net using the following commands in XDC:

set_property MAX_FANOUT 100 [get_cells -hierarchical *ce_predicted_reg*]
set_property MAX_FANOUT 100 [get_nets your_instance_name/U0/i_synth/axi_wrapper/ce_w2c]

The cell in question is the driver of this net.

In the synthesized design, register replication does occur and the fanout is reduced from 2565 to 557.

However the MAX_FANOUT property is not honored.

There are some cells (including the IP interface) that have DONT_TOUCH set to TRUE, but the net's driver and load hierarchies are not involved.

Why is the MAX_FANOUT attribute not enforced?


The MAX_FANOUT constraints are applied to signals that are inside Xilinx IPs.

This is legal, but the problem is that several hierarchies inside the IP have security attributes which causes the hierarchies to remain fixed.

Because of this, when signals with MAX_FANOUT attributes go into or out of hierarchies with hard limits, the replication can not happen.

This is why in this case the fanout limits are not going as far as the constraint.

They can replicate up to the level of a hard hierarchy but cannot go through it.

As a work-around, you can use the following command to force the drivers of the specified net to be replicated.

phys_opt_design -force_replication_on_nets [get_nets net_name] 
AR# 65212
Date 08/28/2015
Status Active
Type General Article
  • Vivado Design Suite
  • Fast Fourier Transform