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AR# 65219

RLDRAM3 IP - older versions of MIG UltraScale RLDRAM IP cause critical warnings in 2015.3

Description

Version Found: RLDRAM v1.0

Version Resolved: See (Xilinx Answer 58435)

A new DRC check has been added in Vivado 2015.3 on usage of the FIFO36E2 primitive.

It will cause critical warnings if an older MIG UltraScale RLDRAM3 IP is brought into Vivado 2015.3 without upgrading to the latest IP version. 

The following CRITICAL WARNING might be seen:

CRITICAL WARNING: [DRC AVAL-247] Independent_clock_check: The FIFO36E2 cell u_af has CLOCK_DOMAINS=INDEPENDENT. However the two clock pins, RDCLK and WRCLK, are driven by the same driver. The expected property value for CLOCK_DOMAINS for this clocking connectivity is COMMON. Improperly setting this attribute can impact simulation, optimization, and timing for the FIFO resulting in incorrect simulation behavior, potential loss of performance, and increase in power.

Solution

To resolve the critical warning, upgrade the IP to RLDRAM3 v1.0 in Vivado 2015.3.

If you are unable to upgrade the IP, please contact Xilinx Technical Support through the Xilinx Service Portal:

http://www.xilinx.com/support/service-portal.html

Revision History:

08/14/2015 Initial Release

Linked Answer Records

Master Answer Records

AR# 65219
Date Created 08/14/2015
Last Updated 10/06/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale