Core latches receive data 1 cycle later than expected in Standard Master Mode when CPHA = 1 and CPOL = 0, or CPHA =0 and CPOL = 1.
It appears version 3.2 rev 2 of the AXI QUAD SPI has an extra FD flip-flop in the IO1 data path.
Why is this the case?
This issue affects the 2014.3 or later versions of the core.
The Core RTL is fixed to avoid bit shift in Standard master mode with SCK = 2 when CPHA =1 and CPOL=0, or CPHAS=0 and CPOL=1.
Work-around: If possible, reducing the core SCK ratio to 4 or more in CPHA = 0 and CPOL =0, or CPHA = 1 and CPOL = 1 mode helps in the SPIx1 interface.
Fix: the RTL is fixed in the Vivado 2015.3 release for this issue.