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AR# 65225

2014.4/2015.1 - AXI Quad SPI V3.2 - Does not function in SPIx1 mode; why?


Core latches receive data 1 cycle later than expected in Standard Master Mode when CPHA = 1 and CPOL = 0, or CPHA =0 and CPOL = 1.

It appears version 3.2 rev 2 of the AXI QUAD SPI has an extra FD flip-flop in the IO1 data path.

Why is this the case?


This issue affects the 2014.3 or later versions of the core. 

The Core RTL is fixed to avoid bit shift in Standard master mode with SCK = 2 when CPHA =1 and CPOL=0, or CPHAS=0 and CPOL=1.

Work-around: If possible, reducing the core SCK ratio to 4 or more in CPHA = 0 and CPOL =0, or CPHA = 1 and CPOL = 1 mode helps in the SPIx1 interface.

Fix: the RTL is fixed in the Vivado 2015.3 release for this issue.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54408 IP Release Notes and Known Issues for LogiCORE IP AXI Quad SPI for Vivado 2013.4 and older tool versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
64257 Embedded - Boot and Configuration N/A N/A
AR# 65225
Date 09/11/2015
Status Active
Type Known Issues
  • Artix-7
  • Kintex UltraScale
  • Kintex-7
  • More
  • Kintex-7Q
  • Artix-7Q
  • Virtex-7
  • Virtex-7Q
  • Virtex UltraScale
  • Less
  • Vivado Design Suite
  • AXI Serial Peripheral Interface
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