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AR# 65242

MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2013.1 tool and later versions


This answer record contains the Release Notes and Known Issues for the MIPI CSI-2 Receiver Subsystem and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

IP MIPI CSI-2 Receiver Subsystem Page:



General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado.

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core VersionVivado Tools Version
v2.1 (Rev. 1)2016.4
v2.0 (Rev. 1)2016.2

General Guidance

The table below provides Answer Records for general guidance when using the MIPI CSI-2 Receiver Subsystem.

Table 2: General Guidance

Article NumberArticle Title

Known and Resolved Issues

The following table provides known issues for the MIPI CSI-2 Receiver Subsystem , starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 69057)Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem?v2.1 (Rev. 1)v2.2
(Xilinx Answer 67960)Why do I get a Critical Warning (Vivado 12-1433) when implementing the IP in OOC mode in the Vivado IDE?v2.1N/A
(Xilinx Answer 67793)Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave?v2.0 (Rev. 1)v2.1
(Xilinx Answer 66994)Why do I get a CRITICAL WARNING about 'vfb_v1_0_2_viv_fifo_gen.v' when instantiating multiple MIPI CSI-2 Receiver Subsystems on my design?v2.0v2.0 (Rev. 1)
(Xilinx Answer 65741)Why do I see [Designutils 20-1280] when opening a design in the Vivado elaboration mode?v1.0v2.0

Revision History:

04/05/2017Added v2.1 (Rev.1) and v2.2 to Version Table and (Xilinx Answer 69057).
10/05/2016Added v2.0 (Rev.1) and v2.1 to Version Table, (Xilinx Answer 67793) and (Xilinx Answer 67960) .
04/06/2016Added v2.0 to Version Table and Added (Xilinx Answer 66994).
10/20/2015Added (Xilinx Answer 65741)
09/30/2015Initial Release


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Associated Answer Records

AR# 65242
Date 04/26/2017
Status Active
Type Release Notes
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Virtex UltraScale+
  • MIPI D-PHY Controller