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AR# 65242

MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions

Description

This answer record contains the Release Notes and Known Issues for the MIPI CSI-2 Receiver Subsystem and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

IP MIPI CSI-2 Receiver Subsystem Page:

https://www.xilinx.com/products/intellectual-property/ef-di-mipi-csi-rx.html

Solution

General Information

Supported Devices can be found in the following three locations:

For a list of new features and added device support for all versions:

  • Subsystem or IP - See the Changelog included with the core in Vivado.
  • Subsystem or IP - Click on the Changelog links below.
  • Standalone Software Drivers - See the Chagelog included with the Doxygen Drivers in the Xilinx SDK
  • Standalone Software Drivers - Github Software Driver Repo

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Table 1: Version

Core VersionVivado Tools VersionIP ChangelogIP Patches
v3.0 (Rev. 2)2018.1
v3.0 (Rev. 1)2017.4(Xilinx Answer 70386)
v3.02017.3(Xilinx Answer 69903)
v2.2 (Rev. 1)2017.2(Xilinx Answer 69326)(Xilinx Answer 69431)
v2.22017.1(Xilinx Answer 69055)
v2.1 (Rev. 1)2016.4(Xilinx Answer 68369)
v2.12016.3(Xilinx Answer 68021)
v2.0 (Rev. 1)2016.2(Xilinx Answer 67345)
v2.02016.1(Xilinx Answer 66930)
v1.02015.3(Xilinx Answer 65570)

General Guidance

The table below provides Answer Records for general guidance when using the MIPI CSI-2 Receiver Subsystem.

Table 2: General Guidance

Article NumberArticle Title
(Xilinx Answer 70308)Which licenses are needed to generate the MIPI CSI-2 Application Example Design?
(Xilinx Answer 69322)Why do I get Vivado implementation errors after changing the Calibration Mode to Auto?

Known and Resolved Issues

The following table provides known issues for the MIPI CSI-2 Receiver Subsystem , starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Table 3: IP

Article NumberArticle TitleVersion FoundVersion Resolved
(Xilinx Answer 70581)Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices?v3.0 (Rev. 1)v3.0 (Rev. 2)
(Xilinx Answer 69441)Why is the MIPI CSI-2 Receiver with Clock/Data skew calibration set to Auto/Fixed, failing during implementation?v2.1 (Rev. 1)N/A
(Xilinx Answer 69057)Why is an SOTsynchs error generated from MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem?v2.1 (Rev. 1)v2.2
(Xilinx Answer 67960)Why do I get a Critical Warning (Vivado 12-1433) when implementing the IP in OOC mode in the Vivado IDE?v2.1N/A
(Xilinx Answer 67793)Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave?v2.0 (Rev. 1)v2.1
(Xilinx Answer 66994)Why do I get a CRITICAL WARNING about 'vfb_v1_0_2_viv_fifo_gen.v' when instantiating multiple MIPI CSI-2 Receiver Subsystems on my design?v2.0v2.0 (Rev. 1)
(Xilinx Answer 65741)Why do I see [Designutils 20-1280] when opening a design in the Vivado elaboration mode?v1.0v2.0

Revision History:

04/04/2018Added v3.0 (Rev.2) to Version Table and (Xilinx Answer 70581)
03/02/2018Added (Xilinx Answer 70308)
02/20/2018Added v3.0 and v3.0 (Rev.1) to Version Table.
07/07/2017Added (Xilinx Answer 69441).
06/20/2017Added v2.2 (Rev.1) to Version Table and (Xilinx Answer 69322).
04/05/2017Added v2.1 (Rev.1) and v2.2 to Version Table and (Xilinx Answer 69057).
10/05/2016Added v2.0 (Rev.1) and v2.1 to Version Table, (Xilinx Answer 67793) and (Xilinx Answer 67960) .
04/06/2016Added v2.0 to Version Table and Added (Xilinx Answer 66994).
10/20/2015Added (Xilinx Answer 65741)
09/30/2015Initial Release

 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
56852 Xilinx Multimedia, Video and Imaging Solution Center - Top Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
65741 IP MIPI CSI-2 Receiver Subsystem v1.0 - Why do I see an a [Designutils 20-1280] when opening a design in Vivado's elaboration mode? N/A N/A
66994 MIPI CSI-2 Receiver Subsystem v2.0 - Why do I get a CRITICAL WARNING about 'vfb_v1_0_2_viv_fifo_gen.v' when instantiating multiple MIPI CSI-2 Receiver Subsystems on my design? N/A N/A
67793 MIPI CSI-2 Receiver Subsystem v2.0 (Rev. 1) - Why do I see timing failing on the video_aresetn when using two CSI-2 Receiver Subsystems with one as a master and one as a slave? N/A N/A
67960 MIPI CSI-2 Receiver Subsystem v2.1 - Why do I get a Critical Warning (Vivado 12-1433) when implementing the IP in OOC mode in the Vivado IDE? N/A N/A
69057 LogiCORE IP MIPI D-PHY Controller v3.0 (Rev. 1) - Why is an SOTsynchs error generated from the MIPI DPHY RX IP or MIPI CSI-2 Rx Subsystem? N/A N/A
68810 2016.4 LogiCORE IP MIPI D-PHY Controller v3.0 (Rev. 1) - Patch Updates for the LogiCORE IP MIPI D-PHY Controller v3.0 (Rev. 1) N/A N/A
69322 LogiCORE IP MIPI CSI-2 RX Subsystem - Why do I get Vivado implementation errors after changing the Calibration Mode to Auto? N/A N/A
69431 2017.2 LogiCORE IP MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) - Patch Updates for the LogiCORE IP MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) N/A N/A
69441 MIPI CSI-2 Receiver Subsystem v2.2 (Rev.2) - Why is the MIPI CSI-2 Receiver with Clock/Data skew calibration set to Auto/Fixed, failing during implementation? N/A N/A
69525 MIPI CSI-2 TX Subsystem - How is the Frame End generated? N/A N/A
69530 LogiCORE MIPI D-PHY and MIPI CSI-2 RX Subsystem - How much margin is in the MIPI D-PHY RX line rate settings? N/A N/A
69766 LogiCORE IP MIPI D-PHY Controller v3.1 (Rev. 1) - When using MIPI D-PHY TX, why do we have skewed SoT signal between lanes? N/A N/A
70196 LogiCORE IP MIPI D-PHY v4.0 - On 7 Series Devices, High-Speed Lanes are unconnected in the synthesized design with Auto Calibration Auto and external IDELAYCTRL N/A N/A
70308 MIPI CSI-2 Receiver Subsystem - Which licenses are needed to generate the MIPI CSI-2 Application Example Design? N/A N/A
70581 LogiCORE IP MIPI D-PHY Controller v4.0 (rev.1) (or MIPI CSI-2 Receiver Subsystem v3.0 (Rev. 1)) - Why do I see SoT/ECC/CRC errors on MIPI RX IP targeting UltraScale+ devices? N/A N/A

Associated Answer Records

AR# 65242
Date 04/09/2018
Status Active
Type Release Notes
Devices
  • Zynq UltraScale+ MPSoC
  • Kintex UltraScale+
  • Virtex UltraScale+
IP
  • MIPI D-PHY
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