We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6527

V2.1, V1.5i COREGEN, FOUNDATION: Virtex block RAM generated by CORE Generator does not simulate initial values properly in Foundation functional simulation


Keywords: Virtex, block ram, simula, coregen, CORE Generator,
Foundation, functional

Urgency: Standard

General Description: When Coregen is used to create block RAM and is
initialized using a .COE file, the RAM does not initialize properly in Foundation
functional simulation. Zeros appear on the output of the block ram,
regardless of the inital values set in the .COE file.


A workaround is to run the design through Translate in the Design Manager,
then run a Checkpoint Gate level Simulation from the Foundation Project
Manager (Tools --> Simulation/Verification --> Checkpoint Gate Simulation
Control). This will include the initial values taken from the .COE file, and
properly simulate the design in the Foundation Simulator.
AR# 6527
Date Created 05/17/1999
Last Updated 06/13/2002
Status Archive
Type General Article