UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65313

LogiCORE IP JESD204 PHY v2.0 - MMCM_Locked output port not generated for JESD PHY core generated with the "Shared Logic in Core" option

Description

I am using the LogiCORE IP JESD204 PHY v2.0 (2015.1).

If the JESD PHY core is generated for an Artix-7 device in IPI with the "Shared Logic in Core" option selected, mmcm_reset and mmcm_lock pins are missing from the generated core.

Solution

To work around this limitation with the "Shared Logic in Core" option selected, use the clocking wizard and connect the mmcm reset out of the second PHY core with Shared Logic in the Example Design.

Connect the locked output from the clocking wizard to the mmcm_lock pin.

The clocking module of the PHY with "Shared Logic in Core" can be checked for settings and connections of the mmcm.

The description of mmcm_lock is added to JESD204 PHY v3.0 LogiCORE IP Product Guide.

This is resolved in JESD204 PHY v3.0 (Vivado 2015.3).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
61911 LogiCORE IP JESD204 PHY core - Release Notes and Known Issues N/A N/A
AR# 65313
Date Created 09/01/2015
Last Updated 09/03/2015
Status Active
Type General Article
IP
  • JESD204