To work around this limitation with the "Shared Logic in Core" option selected, use the clocking wizard and connect the mmcm reset out of the second PHY core with Shared Logic in the Example Design.
Connect the locked output from the clocking wizard to the mmcm_lock pin.
The clocking module of the PHY with "Shared Logic in Core" can be checked for settings and connections of the mmcm.
The description of mmcm_lock is added to JESD204 PHY v3.0 LogiCORE IP Product Guide.
This is resolved in JESD204 PHY v3.0 (Vivado 2015.3).