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AR# 65349

Embedded Linux - How Do I Configure U-Boot MDC Frequency According to Zynq-7000 clk1x ?

Description

The MDC clock frequency should not be more than 2.5MHz.

However, U-Boot sets a fixed MDC divider for Zynq in u-boot-xlnx/drivers/net/zynq_gem.c

#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */

Because U-Boot does not configure clk1x, the generated MDC may be more than 2.5MHz in some situations.  

How can I avoid this?

Solution

The most robust solution is to calculate clk1x ahead of time, and then modify ZYNQ_GEM_NWCFG_MDCCLKDIV in the zynq_gem.c file to generate a correct MDC.
AR# 65349
Date Created 09/07/2015
Last Updated 09/09/2015
Status Active
Type General Article
Devices
  • Zynq-7000
Tools
  • PetaLinux