UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6537

Simulation, UniSim, SimPrim - How do I use the "glbl.v" module in a Verilog simulation?

Description

How do I use the "glbl.v" module in a Verilog simulation?

Solution

The "glbl.v" module connects the Global Set/Reset and Global Tristate signals to the design. In order to properly reset the design in a Verilog simulation, the "glbl.v" module must be compiled and loaded along with the design. The "glbl.v" module is located at "$XILINX/verilog/src/glbl.v".

Using 6.1i design tools and later

In the 6.1i design tools, the "glbl.v" module was modified to automatically pulse GSR (FPGA Global Set/Reset) and PRLD (CPLD Global Set/Reset) for the first 100 ns of simulation. Code was also added to automatically pulse Global Tristate (GTS), but the default pulse is 0 ns.

For exact commands on how to compile and load the "glbl.v" in ModelSim, see the following solutions:

(Xilinx Answer 1078) - Behavioral Simulation

(Xilinx Answer 10177) - Post-PAR Timing Simulation

For additional information, reference the Synthesis and Simulation Design Guide:

http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
In Chapter 6, Verifying Your Design, there is a section on "Understanding the Global Reset and Tristate for Simulation."

Using 5.1i/5.2i design tools and earlier versions

Prior to the 6.1i release, the "glbl.v" module did not automatically pulse the GSR or PRLD signal. It is therefore necessary to drive GSR or PRLD and/or GTS from the testbench. This is the code that needs to be added to the testbench:

reg GSR;

assign glbl.GSR = GSR;

reg GTS;

assign glbl.GTS = GTS;

initial begin

GSR = 1;

#100 GSR = 0;

end

NOTE 1: For CPLD designs, replace GSR with PRLD in above the code.

NOTE 2: GTS can also be driven, but it is generally not necessary unless you are doing a board-level simulation.

For exact commands on how to compile and load the "glbl.v" in ModelSim, see the following solutions:

(Xilinx Answer 1078) - Behavioral Simulation

(Xilinx Answer 10177) - Post-PAR Timing Simulation

For additional information, reference the Synthesis and Simulation Design Guide:

http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
In Chapter 6, Verifying Your Design, there is a section on "Understanding the Global Reset and Tristate for Simulation."

AR# 6537
Date Created 08/21/2007
Last Updated 03/04/2013
Status Active
Type General Article