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AR# 65372

DDR4/DDR3 IP - Vivado GUI Simulations fail with data errors when using VCS simulator

Description

Version Found: DDR4/DDR3 v1.0

Version Resolved: See (Xilinx Answer 58435)

For some DDR4/DDR3 IP configurations the VCS simulator will fail with the following data errors:

sim_tb_top.mem_model_x4.memRank[0].memModel[0].u_ddr3_x4.data_task: at time 6046689.0 ps ERROR: DQS   bit           0 latching edge required during the preceding clock period.
sim_tb_top.mem_model_x4.memRank[0].memModel[0].u_ddr3_x4.data_task: at time 6046689.0 ps ERROR: DQS_N bit           0 latching edge required during the preceding clock period.
sim_tb_top.mem_model_x4.memRank[0].memModel[3].u_ddr3_x4.dqs_neg_timing_check: at time 6047862.0 ps ERROR: tDQSH violation on DQS   bit          0
sim_tb_top.mem_model_x4.memRank[0].memModel[3].u_ddr3_x4.dqs_neg_timing_check: at time 6047862.0 ps ERROR: tDQSH violation on DQS_N bit          0

 ERROR: Expected data=010801080108010801080108010801080108010801080108, Received data=000800080000000000080008000000000008000800000000 @ 7002551.0 ps
ERROR: Expected data=011001100110011001100110011001100110011001100110, Received data=001000100000000000100010000000000010001000000000 @ 7015920.0 ps
ERROR: Expected data=011801180118011801180118011801180118011801180118, Received data=001800180000000000180018000000000018001800000000 @ 7029288.0 ps
100 Writes and 100 Reads to the memory completed
TEST FAILED: DATA ERROR

This issue only occurs with VCS simulators when run from Vivado GUI. 

All other supported simulators and VCS run stand alone are not affected.

Solution

The errors are caused by an issue with the VCS "-debug_pp" switch and not with Vivado or the DDR4/DDR3 IP.

To work around the issue when using the IP Example design, follow the steps below:

  1. Generate the DDR4/DDR3 IP

  2. Open the IP Example Design

  3. Under Simulation Settings, Select VCS simulator as the Simulator
    • Map the libraries for VCS
    • Select the option to Generate scripts only
  4. Go to the "example_design/example_design.sim/sim_1/behav" directory

  5. Open the elaborate.sh file and modify the line from
    "vcs_opts="-full64 -debug_pp -t ps -licqueue -l elaborate.log""
    Modify the line to
    "vcs_opts="-full64 -debug_all -t ps -licqueue -l elaborate.log""

  6. Run ./compile.sh

  7. Run ./elaborate.sh

  8. Run ./simulate.sh


Revision History
:

09/30/2015 - Initial Release

AR# 65372
Date Created 09/09/2015
Last Updated 10/12/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale