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AR# 65402

Soft Error Mitigation (SEM) IP - When performing error injection into configuration memory high performance interfaces may experience bit errors.

Description

Quick successive error injections into unrelated or non-essential configuration memory can cause errors on a design's I/O interface (for example, increased bit error rate on a GT interface or any high speed memory interface)

Solution

The Soft Error Mitigation (SEM) IP's error injection feature is a tool provided to test the resiliency of the design and to emulate the design's behavior when a real soft error occurs.

An Increased error rate on I/O interfaces when SEM IP is used to perform frequent error injections might be an indication that the design's jitter budget is insufficient or too tight.

Please verify that you are following the recommended clocking schemes and other design guidelines to minimize the jitter in the design.

For more error injection guidance:

1) See (Xilinx Answer 61241)

2) For UltraScale see PG187 (2015.3 onwards), Chapter 4: Integration and Validation section and Appendix C: Error Injection Guidance

3) For 7 series see PG036 - (2015.3 onwards) , Chapter 4: Integration and Validation section

AR# 65402
Date Created 09/14/2015
Last Updated 10/23/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale