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AR# 65410

Vivado Synthesis: Does Vivado Synthesis support Register Balancing/Retiming?


Please refer to this Answer Record for help with Register Balancing.

  • Does Vivado synthesis support Register Balancing/Retiming?
  • How do I enable retiming in Vivado synthesis?


Register balancing or Retiming enables a flip-flop retiming algorithm in the Vivado synthesis process.

Retiming will improve the design timing performance by moving flip-flops and latches across the logic to increase clock frequency.

Starting with Vivado 2015.3, retiming can be enabled in Vivado synthesis using the following Tcl command:

set_param synth.elaboration.rodinMoreOptions "rt::set_parameter synRetiming true"

Starting from Vivado 2016.1, a new option "-retiming" is added into Synthesis settings and synth_design command as a formal support of retiming.

AR# 65410
Date Created 09/15/2015
Last Updated 04/26/2016
Status Active
Type General Article
  • FPGA Device Families
  • Vivado Design Suite - 2015.3
  • Vivado Design Suite