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AR# 65418

Vivado Synthesis - Verilog port direction problem in RTL not messaged by Vivado


When synthesizing a design with several hierarchies, much of the logic is optimized after opt_design.

There can be a disconnect between hierarchies, caused by the wrong direction being assigned in on of the RTL files. However, Vivado Synthesis does not report a warning about this issue.

In the following example, a Verilog port which should have been defined as an output, was mistakenly set as an input.

This caused the net within this module to have two drivers, but no output.

Also, this output was supposed to drive other logic in another hierarchy which eventually was optimized away.

input wire i_vs,
// input wire [4*DATA_WIDTH:0] o_connect, // ORIGINAL PORT DIRECTION
output wire [4*DATA_WIDTH:0] o_connect, // CORRECCT PORT DIRECTION


There is no plan to provide an error message for this situation.

Even though the direction and inferred connection were not expected, this is still legal syntax in Verilog.

To work around this issue, trace the opt_design trimming by enabling the -verbose option, to find the root cause of similar connection issues.

AR# 65418
Date Created 09/15/2015
Last Updated 10/16/2015
Status Active
Type Known Issues
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • More
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Less