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AR# 65421

UltraScale DDR3 - tIS memory model violations on ADDR and BA occur when simulating DDR3 example_tb testbench

Description

Version Found: v5.0

Version Resolved; See (Xilinx Answer 58435)

When running an UltraScale DDR3 simulation using the provided example_tb testbench, the memory model flags the following errors:

# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  4 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  6 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3151266.0 ps ERROR:   tIS violation on ADDR  8 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3176972.0 ps ERROR:   tIS violation on ADDR 10 by 35.0 ps
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3703942.0 ps ERROR: CWL =           9 is illegal @tCK(avg) = 1071.076172
# sim_tb_top.mem_model_x8.memModel[0].u_ddr3_x8.main: at time 3836756.0 ps ERROR:   tIS violation on BA 0    by 35.0 ps

Solution

The violation reported is that address/bank is toggling at the rising edge of the DRAM clock, which the model reports as a tIS violation.

However, the model is flagging the violation on a DESELECT command which has "don't care" for address/bank.

These errors can be safely ignored.

Revision History:

09/30/2015 Initial Release
AR# 65421
Date Created 09/15/2015
Last Updated 10/06/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale