Version Found: v5.0
Version Resolved; See (Xilinx Answer 58435)
When running an UltraScale DDR3 simulation using the provided example_tb testbench, the memory model flags the following errors:
The violation reported is that address/bank is toggling at the rising edge of the DRAM clock, which the model reports as a tIS violation.
However, the model is flagging the violation on a DESELECT command which has "don't care" for address/bank.
These errors can be safely ignored.