The Virtex UltraScale FPGA VCU108 Evaluation Kit Checklist is useful to debug board-related issues and to determine if applying for a Board RMA is the next step.
Before working through the VCU108 Board Debug Checklist, please review (Xilinx Answer 62603) - Virtex UltraScale VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record, as the issue you are faced with may be covered there.
Default Switch and Jumper Settings for the VCU108 are:
Start from a known safe scenario by verifying the default Switch and Jumper settings. You can then set switches / jumpers for your application.
a. DIP Switch Default Settings:
b. DIP Switch SW16 Mode Settings:
The mode switches M2, M1, and M0 are on SW16 positions 3, 4, and 5, respectively. The FPGA default mode setting M[2:0] = 101 selects the JTAG configuration mode.
c. Default Jumper Settings:
The default jumper setttings are listed below. The board header jumper locations can be found in the Figure under the table.
The status of the Power-ON LEDs is an indication of board health.
a. Check the status of the following LEDs at Power-ON:
b. Ethernet PHY status LEDs.
These LEDs are visible on the left edge of the VCU108 board when it is installed into a PCIe slot in a PC chassis.
The two PHY status LEDs are integrated into the metal frame of the P3 RJ-45 connector, as shown below:
c. Voltage and current monitoring and control for the Maxim Integrated power system is available through either the VCU108 system controller or via the Maxim Integrated PowerTool software graphical user interface.
d. If 12V Power LED (DS26 on the KCU105) is not Green upon power up, then 12VDC is not being delivered to the KCU105 power input connector.
Follow these steps:
The VCU108 uses a USB A-to-micro-B cable plugged into the VCU108 Digilent USB-to-JTAG module, U115, through connector J106.
A 2-mm JTAG header (J3) is also provided in parallel for access by Xilinx download cables such as the Platform Cable USB II.
a. USB A-to-micro-B cable:
If the three items highlighted in the figure below are visible in Device Manager, this confirms that your USB cable is operational and has been correctly identified.
If the above steps do not enable you to connect, please review the Support Webpage for your available Support options.
To check to see that the JTAG chain is initialized correctly, follow this JTAG Initialization Test Case:
1. Remove any FMC cards from VCU108.
2. Set the mode switch SW15 for JTAG mode (101).
3. Power up VCU108 on the bench (not in a PC chassis).
4. Connect the Digilent USB A-to-micro B cable to the VCU108 (through the Digilent onboard USB-to-JTAG configuration logic module - U115 - through header J106).
5. Check that the Digilent device shows up in the Device Manager.
6. Ensure Xilinx tools (Vivado 2015.1 or later - preferably the latest version of tools that support the VCU108) are correctly installed.
7. Launch Vivado Hardware Manager - is the cable identified correctly?
If following the above steps does not allow you to initialize the JTAG chain, please disconnect the Digilent USB A-to-micro-B cable from the board and PC.
Connect the Platform Cable USB to header J3, and connect to your PC.
Ensure Xilinx tools (preferably the latest version of tools that support the VCU108) are correctly installed.
Launch Vivado Hardware Manager - is the cable identified correctly?
If following the above steps does not allow you to initialize the JTAG chain, please review the Support Webpage for your available Support options.
If the JTAG chain initializes okay but JTAG configuration fails, check the following:
a) Verify the mode switch settings for JTAG configuration mode:
SW15-2 (M2) 1
SW15-3 (M1) 0
SW15-4 (M0) 1
b) In Vivado Hardware Manager, select a lower cable frequency and re-attempt configuration.
c) Pulse the PROG push button on the VCU108 (SW4).
Pulsing PROG will clear out any problems caused by power up ramp rate issues to the FPGA.
d) Review (Xilinx Answer 34904) - Xilinx Configuration Solution Center.
The Configuration Solution Center is available to address all questions related to Configuration.
If the above steps fail to enable JTAG configuration, please review the Support Webpage for your available Support options.
If the VCU108 configures correctly, but the PCIe interface does not operate as expected, check the following:
a) Do NOT plug a PC ATX power supply 6-pin connector into J15 on the VCU108 board.
The ATX 6-pin connector has a different pinout than J15.
Connecting an ATX 6-pin connector into J15 will damage the VCU108 board and void the board warranty.
To install and power the board correctly, follow the instructions given in (UG1066) VCU108 Evaluation Board User Guide - Appendix E - Board Setup.
b) Check J74, lane width, is set correctly for your application.
c) See one of the following Answer Records, covering Known Issues for PCI Express, including Virtex UltraScale:
(Xilinx Answer 57945) - UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.3 and newer tools versions.
d) Download and run the VCU108 PCIe Example Design, whichever version is appropriate for your silicon and software version.
It is recommended to always use the latest version of software which supports the VCU108, and associated version of the VCU108 PCIe Example Design.
Follow the associated PDF.
All are available from the VCU108 Example Designs page.
e) Read the VCU108 PCIe Example Design document: VCU108 PDF xtp366.pdf and follow the instructions within.
f) Review (Xilinx Answer 34536) - Xilinx Solution Center for PCI Express.
The Solution Center for PCI Express is available to address all questions related to the Xilinx solutions for PCI Express.
If the above steps fail to resolve the PCIe issue, please review the Support Webpage for your available Support options.
7. Interface Tests
(Xilinx Answer 65464) - Virtex UltraScale FPGA VCU108 Evaluation Kit - Interface Test Designs can be run to ensure that the interfaces on the VCU108 are working correctly.
This Answer Record forms part of (Xilinx Answer 43748) - Xilinx Boards and Kits Debug Assistant.
If the above tests fail to resolve the issue, please review the Support Webpage for your available Support options.
8. Known Issues for VCU108
All Known Issues for the Virtex UltraScale FPGA VCU108 Evaluation Kit are listed in (Xilinx Answer 62603) - Virtex UltraScale FPGA VCU108 Evaluation Kit - Known Issues and Release Notes Master Answer Record.
If the issue you are faced with is not listed in the Known Issues and Release Notes Master Answer Record, and the steps above fail to resolve the issue, please review the Support Webpage for your available Support options.
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