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AR# 65431

UltraScale Memory IP - Designs generated pre-v1.0 with "No Buffer" clocking option require path update to CLOCK DEDICTAED ROUTE constraint

Description

Version Found: v1.0

Version Resolved: See (Xilinx Answer 58435)

Starting with the v1.0 release of the UltraScale memory IP, the hierarchy of the IP has been modified, which has moved the clocking infrastructure.

(PG150) includes block diagrams of the new hierarchy.

As a result, if you have memory IP generated before v1.0 with the "No Buffer" option enabled, you will have to change the CLOCK_DEDICATED_ROUTE (CDR) constraints within the user XDC.

The example designs include the appropriate path within the CDR constraints.

Solution

Modify the CLOCK_DEDICATED_ROUTE constraints as follows:

DDR3

2015.3

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

2015.2

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr3_infrastructure/mmcme3_adv_inst/CLKIN1}]

DDR4

2015.3

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

2015.2

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/mmcme3_adv_inst/CLKIN1}]

QDRII+

2015.3

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_qdriip_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

2015.2

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_qdriip_infrastructure/mmcme3_adv_inst/CLKIN1}]

RLDRAM3

2015.3

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_rld3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKIN1}]

2015.2

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_rld3_infrastructure/mmcme3_adv_inst/CLKIN1}]

AR# 65431
Date Created 09/16/2015
Last Updated 10/16/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
IP
  • MIG UltraScale