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AR# 65443

DMA Subsystem for PCI Express - Release Notes and Known Issues for Vivado 2015.3 and newer tool versions

Description

This answer record contains the Release Notes and Known Issues for the DMA Subsystem for PCI Express Core and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This Release Notes and Known Issues Answer Record is for the core generated in Vivado 2015.3 and newer tool versions.

Solution

Supported devices can be found in the following three locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools.
  • PCIe DMA Subsystem Product Guide (PG195)

 

Version Table

This table correlates the core version to the first Vivado design tools release version in which it was included.

Core Version Vivado Tools Version
v4.1 (Rev1) 2018.2
v4.1 2018.1
v4.0 (Rev1) 2017.4
v4.0 2017.3
v3.1(Rev1) 2017.2
v3.1 2017.1
v3.0 (Rev1) 2016.4
v3.0 2016.3
v2.0 (Rev1) 2016.2
v2.0 2016.1
v1.0 (Rev1) 2015.4
v1.0
2015.3

 

Tactical Patch

The following table provides a list of tactical patches for the DMA Subsystem for PCI Express core applicable on corresponding Vivado tool versions.

Answer Record Core Version (After installing the Patch) Tool Version
(Xilinx Answer 66500) v1.0 (Rev. 66500)
2015.4
(Xilinx Answer 67111) v2.0 (Rev. 67111) 2016.1
(Xilinx Answer 67421) v2.0 (Rev. 67421) 2016.2
(Xilinx Answer 68111) v3.0 (Rev. 68111) 2016.3
(Xilinx Answer 68259)
v3.0 (Rev. 68259) 2016.3
(Xilinx Answer 68478) v3.1 (Rev. 68478) 2016.4
(Xilinx Answer 68512) v3.1 (Rev. 68512) 2016.4
(Xilinx Answer 69275) v3.1 (Rev. 69275) 2017.1
(Xilinx Answer 69405) v3.1(Rev. 69405) 2017.2
(Xilinx Answer 70012) v4.0 (Rev. 70012) 2017.3
(Xilinx Answer 70324)
v4.0 (Rev 70324) / v4.0 (Rev 70325)
2017.3/2017.4
(Xilinx Answer 70877) v4.0(Rev. 70877) 2017.4
(Xilinx Answer 71012) v4.0 (Rev.71012) / v4.1 (Rev. 71012) 2017.4/2018.1
(Xilinx Answer 71052)
v4.1 (Rev. 71052)
2018.1
(Xilinx Answer 71147)
v4.1 (Rev. 71147) 2018.1
(Xilinx Answer 71169) v4.1 (Rev. 71169) 2018.1

 

Note:

  • For a given Vivado version, the latest patch consists of fixes in all previous patches for that Vivado version and all also fixes in patches for previous Vivado versions. The table below gives a detailed description of the patches.

Design Advisory

(Xilinx Answer 70838) Design Advisory for AXI SmartConnect with PCI Express IP - Interoperability Issue - Data request upsize causes potential data corruption

Known and Resolved Issues

The following table provides known issues for the DMA Subsystem for PCI Express core, starting with v1.0, initially released in Vivado 2015.3.

Note: The "Version Found" column lists the version the problem was first discovered.

 

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer Record Title Version Found Version Resolved
(Xilinx Answer 71169) Core left shifts the values of MSIX_CAP_TABLE_OFFSET and MSIX_CAP_PBA_OFFSET parameters by 3 bits v4.1 v4.1 (Rev1)
(Xilinx Answer 71147) Tactical patch for issue fixes

  • Bug Fix: Fixed TLP ordering issue on Slave AXI Lite and Slave AXI Interfaces
  • Bug Fix: Fixed Master MemWr and received interrupt ordering issue for AXI Bridge RC configuration 
  • Bug Fix: Fix for CQ NP credits after Partial Reconfiguration
  • Bug Fix: Fix for [Synth 8-488] error when synthesizing XDMA IP with IBERT enabled
  • Bug Fix: Fixed for 7 Series Gen2 DMA hang issue due to TLP drop and incorrect TLP for straddled packets
  • Bug Fix: Fix for Artix-7 GT COMMON placement error, when selecting the GT COMMON to Example Design
  • Bug Fix: Enabled txprgdivresetdone_out port from GT Wizard to fix issue with 125/250 Mhz reference clock with Gen1


v4.1 v4.1 (Rev1)
(Xilinx Answer 71105) MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode v4.1 Work-around Available
(Xilinx Answer 71052) Bridge Mode performance issue in Gen3x8 256 bit Configuration v4.1 v4.1 (Rev1)
(Xilinx Answer 70877) c2h_dsc_byp_ready may deassert permanently in Descriptor Bypass mode v4.0 (Rev1)
v4.1 (Rev1)
(Xilinx Answer 71012) PCIe to DMA Bypass BAR size cannot be set to 32GB when 64Bit enable is selected  v4.0(Rev1) / v4.1
v4.1 (Rev1)
(Xilinx Answer 70324) Tactical patch for issue fixes

Issue 1:


If Max Read Request Size = 128B, MPS= 128B and transfer length= 129B are set, DMA transfer does not complete.
The following issues are seen:


  • For H2C transfer, two Read Requests are created and two completions returned but the second completion does not appear on the AXI bus.
  • For C2H transfer, s_axis_cc_tready is deasserted.

Issue 2:

  • H2C transfer hangs when the AXI data width is 128-bit and 64 bit addressing mode is enabled.

v4.0 / v4.0 (Rev1) v4.1
(Xilinx Answer 70012) Tactical patch for issue fixes and enhancements

DMA / Bridge Subsystem for PCI Express v4.0 - (Vivado 2017.3)
All of the issues listed are for both DMA Mode and Bridge Mode
  • Bug Fix: Corrected MSI-X Table Size to 'h1F (32 vectors).
  • Bug Fix: Corrected CC to TX conversion which was causing register read failures when there is high C2H traffic. (affects 7 Series and Zynq-7000 devices only)
  • Bug Fix: Fixed the receive data for PCIe Hard Block when 64-bit addressing is enabled. (affects 7 Series and Zynq-7000 devices only)
  • Bug Fix: Corrected ext_sys_clk_bufg option. (affects UltraScale+ devices only)
  • Bug Fix: Corrected sys_clk BUFG path in ip_pcie4_uscale_late.xdc file when ext_sys_clk_bufg option is set to TRUE. (affects UltraScale+ devices only)
All of the issues listed are for Bridge Mode only
  • Bug Fix: Allow MSI-X Table and PBA registers to be programmed while MSI-X Enable bit in MSIX Control register is 0.
UltraScale+ PCI Express Integrated Block v1.3 - (Vivado 2017.3)
  • Bug Fix: Corrected sys_clk BUFG path in ip_pcie4_uscale_late.xdc file when ext_sys_clk_bufg option is set to TRUE
  • Bug Fix: Corrected multicycle path constraints for design with 512-bit AXI Stream interfaces.
v4.0
v4.0(Rev1)
 
(Xilinx Answer 69405) Tactical patch for issue fixes and enhancements

DMA / Bridge Subsystem for PCI Express v3.1 (Rev. 1) - (Vivado 2017.2)
All of the issues listed are for both DMA Mode and Bridge Mode
  • Bug Fix: Added missing ports for 'Include GT Wizard in Example Design' mode
  • Bug Fix: Corrected GT DRP address width for UltraScale+ device family
  • Bug Fix: PIO failure for 'Include GT Wizard in Example Design' mode
  • Bug Fix: Updated GT Wizard QPLL attributes
  • Bug Fix: CPLL CAL inclusion for 'Include GT Wizard in Example Design' mode'
  • Bug Fix: Corrected MSI-X Table Size to 'h1F (32 vectors)
  • Feature Enhancement: Added option to enable external BUFG_GT/SYNC for sys_clk
  • Feature Enhancement: Moved phy_clk module in support wrapper when selecting 'Include GT Wizard in Example Design mode'
  • Feature Enhancement: New GT Sharing modes - GT Common in Example Design
All of the issues listed are for Bridge Mode only
  • Bug Fix: Allow MSI-X Table and PBA registers to be programmed while MSI-X Enable bit in MSIX Control register is 0.
UltraScale+ PCI Express Integrated Block v1.2 (Rev. 1) - (Vivado 2017.2)
  • Bug Fix: Updated GT Wizard QPLL attributes
  • Bug Fix: CPLL CAL inclusion for 'Include GT Wizard in Example Design' mode'
  • Bug Fix: PIO failure for 'Include GT Wizard in Example Design' mode
  • Feature Enhancement: Added option to enable external BUFG_GT/SYNC for sys_clk
  • Feature Enhancement: Moved phy_clk module in support wrapper when selecting Include GT Wizard in Example Design mode
  • Feature Enhancement: New GT Sharing modes - GT Common in Example Design
v3.1(Rev1)
v4.0
 
(Xilinx Answer 69275) Support for x8gen3 in -2LV UltraScale devices v3.1 v3.1(Rev1)
(Xilinx Answer 68512) Tactical patch for issue fixes and enhancements

  • Issue with generation of ack for interrupts when multiple MSI-X vectors are pointing to the same MSI-X entry
  • Issue with PCIEBAR translation for BYPASS BAR
  • Issue with the XDMA_CONTROL parameter when AXI-LITE BAR is set to 64 bits
  • Issue with the interrupts when only MSI-X is selected for UltraScale+ devices
  • Issue with the Dword alignment when Bridge - Rootport mode is selected
  • Issue with the output signal axi_aresetn where it is being generated based on axi_aresetn from dma_top; it is now generated based on user_reset
  • Issue with simulations where 256bit data was compared for 512bit simulations
  • Added support for 128bytes DMA transactions
  • Issue with the continuous assertion of usr_irq signal in the legacy interrupt mode.
  • Freed-up reserved 64K BAR space when MSI-X is not enabled in AXI_Bridge mode

v3.0 (Rev1) v3.1
(Xilinx Answer 68478) x16 Support in xczu7ev (fbv900 and ffvc1156) Devices v3.0 (Rev1) v3.1
(Xilinx Answer 68617) x16 lane support in VCU118 (xcvu9p-flga2104 -2L device) v3.0 (Rev 1) v3.1
(Xilinx Answer 68259) FATAL_ERROR: Vivado Simulator kernel has discovered an exceptional condition from which it cannot recover. Process will terminate. v3.0 v3.0(Rev1)
(Xilinx Answer 68205) Gen3x8 on UltraScale -1, -1L, -1LV, -1H, -1HV devices and 250Mhz user clock support v3.0 v3.0(Rev1)
(Xilinx Answer 68111) Tactical patch for issue fixes

  • Issue with A-symmetric H2C and C2H channel selection
  • Continuous transfer of bigger packets in Gen3x16
  • Extended Tags (256) for UltraScale+
v3.0
v3.0(Rev1)
 
 
(Xilinx Answer 67421) Prefetchable support for 64-bit BAR v2.0(Rev1) V3.0
(Xilinx Answer 66500)
IDLE STOP is not set correctly
v1.(Rev1)
v2.0
(Xilinx Answer 67111) Issue with Legacy Interrupt Mode and MSI-X Table Offset v2.0 v2.0(Rev1)

 

Other Information:

(Xilinx Answer 70706) DMA/Bridge Subsystem for PCI Express (Vivado 2017.4) - Bridge Mode - Root Port - AXI transactions fail when no Endpoint is connected
(Xilinx Answer 71095) DMA / Bridge Subsystem for PCI Express (Bridge Mode - Vivado 2017.4) - AXIBAR and AXIBAR_HIGHADDR are set incorrectly in an IP Integrator design resulting in DECERR during 64-bit S_AXI access
(Xilinx Answer 71105) DMA Subsystem for PCI Express (Vivado 2018.1) - MSI Interrupt FIFO can overflow in Root Port configuration in Bridge Mode

Revision History:

30/09/2015 Initial Release
02/20/2016 Added (Xilinx Answer 66500)
04/13/2016 Updated for 2016.1 Release
06/06/2016 Added (Xilinx Answer 67111)
08/06/2016 Updated for 2016.2 Release
07/29/2016 Added (Xilinx Answer 67421)
10/05/2016 Updated for 2016.3 Release
10/30/2016 Added (Xilinx Answer 68111)
11/16/2016 Added (Xilinx Answer 68205)
11/23/2016 Added (Xilinx Answer 68259)
02/03/2017 Added (Xilinx Answer 68617) / (Xilinx Answer 68478) / (Xilinx Answer 68512)
08/14/2017 Added (Xilinx Answer 69405)
11/23/2017 Added (Xilinx Answer 70012)
02/02/2018 Added (Xilinx Answer 70324)
04/24/2018 Added (Xilinx Answer 71012)
05/01/0218 Added (Xilinx Answer 70877)
05/03/2018 Added (Xilinx Answer 71052)
18/03/2018 Added (Xilinx Answer 71105)
06/07/2018 Added (Xilinx Answer 71147)
06/13/2018 Added (Xilinx Answer 71169)

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 65443
Date 06/19/2018
Status Active
Type Release Notes
IP
  • DMA for PCI Express (PCIe) Subsystem
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