UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 65453

Vivado 2015.x - ERROR: [XSIM 43-3190] The "System Verilog real type port" is not supported yet for simulation

Description

I am getting the following error related to a real type module port:

ERROR: [XSIM 43-3190] File "C:/10323503/Controller_dpi.sv" Line 4 : The "System Verilog real type port" is not supported yet for simulation.

RTL Sample code:

module Controller_dpi(
    input real Controller_U_error_d,
    output real Controller_Y_control_signal
);

When will this be supported?

Solution

Vivado simulator does support real type, but not at a module port. 

This feature is planned to be added in a future release of Vivado.

AR# 65453
Date Created 09/21/2015
Last Updated 10/19/2015
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite