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AR# 65467

Zynq UltraScale+ MPSoC - Boot and Configuration

Description

This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to boot and configuration known issues.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.

Solution

Find all you need to know about booting a Zynq UltraScale+ MPSoC device

(Xilinx Answer 65468) Zynq UltraScale+ MPSoC - Booting a Zynq UltraScale+ MPSoC Device


Top Xilinx Answer Records on Boot and Configuration

(Xilinx Answer 65463) Zynq UltraScale+ MPSoC - What devices are supported for configuration?
(Xilinx Answer 66740) Zynq UltraScale+ MPSoC - What are the PL configuration bitstream lengths for the Zynq UltraScale+ MPSoC devices?

 

Top Xilinx Answer Records on Debugging Programming/Booting

(Xilinx Answer 66436) XSDB is not able to connect to PSU after successfully booting in SD mode on a ZCU102 board
(Xilinx Answer 66437) psu_post_config (from psu_init.tcl) sometimes hangs on a ZCU102 board
(Xilinx Answer 66438) On ZCU102 QSPI24 warm booting hangs if u-boot was previously executed


Known issues for VIVADO programming flash tools

Xilinx Answer Title Tool Version Found Tool Version Resolved
(Xilinx Answer 66715) QSPI programming on an ZCU102 board requires the Zynq UltraScale+ device to boot in JTAG mode 2016.1 TBD

Known issues for XSDK FSBL

Xilinx Answer Title Tool Version Found Tool Version Resolved
(Xilinx Answer 65971) FSBL EL3 stack size is unused 2015.4 2016.1
(Xilinx Answer 66523) Zynq UltraScale+ MPSoC: FSBL for ZCU102 requires I2C interface 2015.4 TBD


Known issues for XSDK Bootgen

Xilinx Answer Title Tool Version Found Tool Version Resolved
(Xilinx Answer 66861) Creating a boot image, the destination of the bitstream should be PL instead of A53 2016.1 2016.2
(Xilinx Answer 65969) Create Boot Image does not support Zynq UltraScale+ MPSoC 2015.4 2016.1

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64375 Xilinx Zynq UltraScale+ MPSoC Solution Center N/A N/A
66183 Zynq UltraScale+ MPSoC Processing System IP - Release Notes and Known Issues N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
65971 2015.4 - Zynq UltraScale+ MPSoC: FSBL EL3 stack size is unused N/A N/A
AR# 65467
Date Created 09/22/2015
Last Updated 05/16/2016
Status Active
Type Solution Center
Devices
  • SoC