This answer record provides an attached document that describes how to connect the Tri-Mode Ethernet operating at 2.5G and a 1000BASE-X PCS/PMA or SGMII core configured for 2500BASE_X in the top level TEMAC example design.
The Vivado version used is 2015.2 and it is targeting a KC705 board.
It also includes a simulation section on running BIST loopback and a Hardware debug section which covers using ILA debug cores in a Vivado flow.
This Example design is intended to help with running simulation and using ChipScope to capture signals on different interfaces to debug Ethernet MAC and SFP+ designs.
The document attached to this answer record has detailed steps to run the simulation and view signals on different interfaces, and to add an ILA core in Vivado for debugging of Ethernet issues on MAC and PHY cores.
The TEMAC is generated with an AXI Lite interface for configuration and Management purposes. The 2500BAXE_X core is generated without an MDIO interface and it is configured via a configuration vector while the status is reported with a status vector.
The Attached zip file contains the design which can used out of the box for simulation and Hardware validation.
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